Low drop-out regulator and display device including the same
A low drop-out (LDO) regulator includes a pass transistor, a feedback circuit, an error amplifier, and a compensation unit. The pass transistor is configured to regulate a power supply and output an output voltage according to a control signal. The feedback circuit is configured to generate a feedback voltage based on the output voltage. The error amplifier is configured to output a comparison signal in response to a reference voltage and the feedback voltage. The compensation circuit is configured to generate a negative capacitance in association with a first node connected to a gate electrode of the pass transistor.
1. A low drop-out (LDO) regulator, comprising:
a pass transistor configured to regulate an input according to a control signal; and
a compensation circuit configured to provide a negative capacitance to a gate node of the pass transistor,
wherein:
the compensation circuit further comprises a source follower circuit connected to an input terminal of a non-inverted amplifier;
the source follower circuit has a transistor comprising:
a first electrode connected to a power supply;
a second electrode connected to a current sink circuit; and
a gate electrode configured to receive the control signal;
the control signal is formed based on feedback associated with the pass transistor, a reference input, and the negative capacitance; and
an absolute value of the negative capacitance is substantially equivalent to a sum of a parasitic capacitance associated with a first node connected to a gate electrode of the pass transistor and a parasitic capacitance between gate and drain electrodes of the pass transistor.
2. A low drop-out (LDO) regulator, comprising:
a pass transistor configured to regulate a power supply and output an output voltage according to a control signal;
a feedback circuit configured to generate a feedback voltage based on the output voltage;
an error amplifier configured to output a comparison signal in response to a reference voltage and the feedback voltage; and
a compensation circuit configured to generate a negative capacitance in association with a first node connected to a gate electrode of the pass transistor,
wherein:
the compensation circuit further comprises a source follower circuit connected to an input terminal of a non-inverted amplifier;
the source follower circuit has a transistor comprising:
a first electrode connected to the power supply;
a second electrode connected to a current sink circuit; and
a gate electrode configured to receive the control signal; and
an absolute value of the negative capacitance is substantially equivalent to a sum of a parasitic capacitance associated with the first node and a parasitic capacitance between gate and drain electrodes of the pass transistor.
3. The LDO regulator of claim 2 , wherein the pass transistor comprises:
a first electrode connected to the power supply;
a second electrode connected to a second node, the second node being configured to output the output voltage; and
the gate electrode configured to receive the control signal.
4. The LDO regulator of claim 2 , wherein:
an inverted terminal of the error amplifier is configured to receive the reference voltage; and
the non-inverted terminal of the error amplifier is configured to receive the feedback voltage.
5. The LDO regulator of claim 2 , wherein:
the pass transistor is connected to a second node, the second node being configured to output the output voltage; and
an effective load capacitance is formed in association with an output terminal of the second node.
6. The LDO regulator of claim 2 , wherein the compensation circuit comprises:
a non-inverted amplifier comprising:
an operational amplifier;
a first resistor; and
a second resistor, the first resistor and the second resistor being connected between an output terminal of the operational amplifier and ground; and
a capacitor connected to the non-inverted amplifier.
7. The LDO regulator of claim 6 , wherein operational bandwidth of the operational amplifier is wider than operational bandwidth of the error amplifier.
8. The LDO regulator of claim 7 , wherein at least one of the first resistor and the second resistor is a variable resistor.
9. The LDO regulator of claim 7 , wherein:
a non-inverted terminal of the operational amplifier is configured to receive a signal corresponding to the control signal; and
an inverted terminal of the operational amplifier is configured to receive a distributed output voltage of the operational amplifier, the distributed output voltage being distributed by the first resistor and the second resistor.
10. The LDO regulator of claim 1 , wherein types of the transistor of the source follower circuit and the pass transistor are different from each other.
11. The LDO regulator of claim 5 , wherein the effective load capacitance is defined by a parasitic capacitance.
12. A display device, comprising:
a display panel comprising gate lines, data lines, and pixels;
a gate driver configured to output a gate signal to the gate lines;
a source driver configured to output data voltage to the data lines; and
a voltage generator configured to:
receive an input voltage;
convert the input voltage to an analog voltage; and
output the analog voltage to at least one of the gate driver and the source driver, wherein:
the voltage generator comprises a direct current (DC)-to-DC converter and a low drop-out (LDO) regulator;
the LDO regulator comprises:
a compensation circuit configured to generate a negative capacitance;
a pass transistor configured to regulate an output of the DC-to-DC converter and to output an output voltage according to a control signal;
an absolute value of the negative capacitance is substantially equivalent to a sum of a parasitic capacitance associated with a first node connected to a gate electrode of the pass transistor and a parasitic capacitance between gate and drain electrodes of the pass transistor;
the compensation circuit comprises a source follower circuit connected to an input terminal of a non-inverted amplifier; and
the source follower circuit has a transistor comprising:
a first electrode connected to a power supply;
a second electrode connected to a current sink circuit; and
a gate electrode configured to receive the control signal.
13. The display device of claim 12 , wherein:
the LDO regulator further comprises:
a feedback circuit configured to generate a feedback voltage in response to the output voltage; and
an error amplifier configured to output a comparison signal in response to a reference voltage and the feedback voltage; and
the compensation circuit is connected to the first node connected to a gate electrode of the pass transistor.
14. The display device of claim 13 , wherein the compensation circuit further comprises:
the non-inverted amplifier comprising:
an operational amplifier;
a first resistor; and
a second resistor, the first resistor and the second resistor being connected between an output terminal of the operational amplifier and ground; and
a capacitor connected to the non-inverted amplifier.
15. The display device of claim 14 , wherein operational bandwidth of the operational amplifier is wider than operational bandwidth of the error amplifier.
16. The display device of claim 14 , wherein at least one of the first resistor and the second resistor is a variable resistor.