IP Library › Granted Patent US 9,983,820
Granted Patent B2
US 9,983,820 · App. 15/084,440 · Granted May 29, 2018

Method for performing data updates

Inventors: Sönke Ostertun (Wedel, DE); Wolfgang Stidl (Hamburg, DE); Raffaele Costa (Eindhoven, NL)
Assignee: NXP B.V.
G06F3/0632G06F3/0619G06F3/0644G06F3/0653G06F3/0685G06F11/1004G06F12/0246G06F12/1009G06F12/1027G06F2212/1032G06F2212/2022G06F2212/7201G06F2212/7204G06F2212/7209
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Quick Facts
Patent No.
US 9,983,820
App. No.
15/084,440
Granted
May 29, 2018
Kind
B2
Abstract

In an embodiment, a method for re-programming memory is disclosed. In the embodiment, the method involves selecting a memory page based on version information and re-programming the selected memory page using cyclic redundancy check (CRC) data for the memory page.

Claims (33)

1. A method for resolving collisions resulting from tearing events when updating memory, the method comprising:

selecting a memory page from a plurality of memory pages pointing to a logical memory page based on version information;

re-programming the selected memory page; and

mapping the selected memory page to the logical memory page.

2. The method of claim 1 , wherein the memory page is further selected based on performance under a quality read operation.

3. The method of claim 1 , further comprising re-programming the selected memory page using cyclic redundancy checked (CRC) data for the memory page obtained by performing a normal read operation of the page.

4. The method of claim 3 , wherein if CRC data for the selected memory page (first memory page) cannot be obtained by a normal read operation:

selecting a second memory page from the plurality of memory pages pointing to the logical memory page; and

re-programming the second memory page using CRC data obtained by performing a normal read operation of the second memory page.

5. The method of claim 1 , wherein the selected memory page is verified with a quality read operation and, if the page cannot be verified, re-programming the memory page.

6. The method of claim 1 , wherein the method further comprises determining if a tearing event has occurred by reading data programmed to a system page before selecting the memory page.

7. The method of claim 1 , wherein a validity check is performed before re-programming the memory page.

8. The method of claim 7 , wherein the validity check is performed by evaluating a validity check flag stored in an XWORD of the memory page.

9. The method of claim 7 , wherein the validity check is performed by comparing CRC data calculated from the memory page to CRC data stored in an XWORD of the memory page.

10. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform steps including:

selecting a memory page from a plurality of memory pages pointing to a logical memory page based on version information; and

re-programming the selected memory page; and

mapping the selected memory page to the logical memory page.

11. The non-transitory computer-readable storage medium of claim 10 , wherein the memory page is further selected based on performance under a quality read operation.

12. The non-transitory computer-readable storage medium of claim 10 , wherein the memory page is selected from a plurality of physical memory pages that are mapped to the same logical memory page.

13. The non-transitory computer-readable storage medium of claim 10 , wherein the non-transitory computer-readable storage medium further comprises instructions for re-programming the selected memory page using cyclic redundancy checked data obtained by performing a normal read operation of the page.

14. The non-transitory computer-readable storage medium of claim 10 , wherein the selected memory page is verified with a quality read operation and, if the page cannot be verified, re-programming the memory page.

15. The non-transitory computer-readable storage medium of claim 10 , wherein if cyclic redundancy checked data for the selected memory page (first memory page) cannot be obtained by a normal read operation:

selecting a second memory page from the plurality of memory pages pointing to the logical memory page; and

re-programming the second memory page using cyclic redundancy checked data obtained by performing a normal read operation of the second memory page.

16. The non-transitory computer-readable storage medium of claim 10 , wherein an occurrence of a tearing event is determined by reading data programmed to a system page before selecting the memory page.

17. The non-transitory computer-readable storage medium of claim 10 , wherein a validity check is performed before re-programming the memory page.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the validity check is performed by evaluating a validity check flag stored in an XWORD of the memory page.

19. The non-transitory computer-readable storage medium of claim 17 , wherein the validity check is performed by comparing CRC data calculated from the memory page to CRC data stored in an XWORD of the memory page.

20. An integrated circuit comprising a processor and memory, the memory containing instructions that, when executed by the processor, perform steps comprising:

selecting a memory page from a plurality of memory pages pointing to a logical memory page based on version information; and

re-programming the selected memory page; and

mapping the selected memory page to the logical memory page.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2016
From: OSTERTUN, SONKE; STIDL, WOLFGANG; COSTA, RAFFAELE
To: NXP B.V.
Reel/Frame 038128/0881 →
Continuity (1)
Related Publication 20170285996A1 · Oct 5, 2017