IP Library › Granted Patent US 9,984,765
Granted Patent B2
US 9,984,765 · App. 15/621,118 · Granted May 29, 2018

Memory circuit with assist circuit trimming

Inventor: Atul Katoch (Kanata, CA)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
G11C29/027G11C11/417G11C17/16G11C17/18G11C29/78
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Quick Facts
Patent No.
US 9,984,765
App. No.
15/621,118
Granted
May 29, 2018
Kind
B2
Abstract

A method includes: examining, by a test engine, whether a first bit of a memory array is functional; in response to the first bit being not functional, storing, by the test engine, address information of the first bit into a memory device; and retrieving, by an assist circuit trimming (ACT) circuit, the address information of the first bit from the memory device to selectively activate at least a first one of a plurality of assist circuits associated with the first bit.

Claims (39)

1. A method, comprising:

examining whether a first bit of a memory array is functional;

when the first bit is not functional, storing address information of the first bit into a memory device; and

retrieving the address information of the first bit from the memory device to selectively activate at least one of a plurality of assist circuits associated with the first bit.

2. The method of claim 1 , wherein the memory device comprises an eFuse device.

3. The method of claim 1 , wherein the examining whether the first bit of the memory array is functional comprises at least one of examining whether writing a first bit data to the first bit and examining whether reading a second bit data from the first bit is successful.

4. The method of claim 1 , further comprising:

examining whether a second bit of the memory array is functional;

when the second bit is not functional, storing address information of the second bit into the memory device; and

retrieving the address information of the second bit from the memory device to selectively activate at least one of a plurality of assist circuits associated with the second bit.

5. The method of claim 4 , wherein the retrieving the address information of the second bit from the memory device to selectively activate at least one of the plurality of assist circuits associated with the second bit is subsequent to the retrieving the address information of the first bit from the memory device to selectively activate at least one of the plurality of assist circuits associated with the first bit.

6. The method of claim 4 , wherein respective timings of the retrieving the address information of the first bit from the memory device to selectively activate at least one of the plurality of assist circuits associated with the first bit and the retrieving the address information of the second bit from the memory device to selectively activate at least one of the plurality of assist circuits associated with the second bit is synchronized with a common clock signal.

7. The method of claim 1 , wherein the plurality of assist circuits associated with the first bit comprises a first assist circuit coupled to the first bit through a respective word line, and a second assist circuit coupled to the first bit through a respective bit line.

8. A method, comprising:

examining, by a test engine, whether a first bit of a memory array is functional;

in response to the first bit being not functional, storing, by the test engine, address information of the first bit into a memory device; and

retrieving, by an assist circuit trimming (ACT) circuit, the address information of the first bit from the memory device to selectively activate at least a first one of a plurality of assist circuits associated with the first bit.

9. The method of claim 8 , wherein the ACT circuit comprises:

a first flip flop coupled to the first bit and the first one of the plurality of assist circuits associated with the first bit.

10. The method of claim 9 , wherein the first flip flop circuit is configured to provide an activation signal to activate the first one of the plurality of assist circuits associated with the first bit.

11. The method of claim 9 , wherein the ACT circuit further comprises:

a second flip flop coupled to the first bit and a second one of a plurality of assist circuits associated with the first bit.

12. The method of claim 8 , wherein the examining whether the first bit of the memory array is functional comprises at least one of examining whether writing a first bit data to the first bit and examining whether reading a second bit data from the first bit is successful.

13. The method of claim 8 , further comprising:

examining, by a test engine, whether a second bit of a memory array is functional;

in response to the second bit being not functional, storing, by the test engine, address information of the second bit into the memory device; and

retrieving, by the ACT circuit, the address information of the second bit from the memory device to selectively activate at least a third one of a plurality of assist circuits associated with the second bit.

14. The method of claim 13 , wherein the retrieving the address information of the second bit from the memory device to selectively activate at least the third one of the plurality of assist circuits associated with the second bit is subsequent to the retrieving the address information of the first bit from the memory device to selectively activate at least the first one of the plurality of assist circuits associated with the first bit.

15. The method of claim 13 , wherein respective timings of the retrieving the address information of the first bit from the memory device to selectively activate at least the first one of the plurality of assist circuits associated with the first bit and the retrieving the address information of the second bit from the memory device to selectively activate at least the third one of the plurality of assist circuits associated with the second bit is synchronized with a common clock signal.

16. A method, comprising:

examining whether a first bit of a memory array is functional;

examining whether a second bit of the memory array is functional;

when the first bit is not functional, storing address information of the first bit into a memory device;

when the second bit is not functional, storing address information of the second bit into the memory device; and

retrieving the address information of the first and second bits from the memory device to sequentially activate at least one of a plurality of assist circuits associated with the first bit and then at least one of a plurality of assist circuits associated with the second bit.

17. The method of claim 16 , wherein the memory device comprises an eFuse device.

18. The method of claim 16 , wherein the examining whether the first bit of the memory array is functional comprises at least one of examining whether writing a first bit data to the first bit and examining whether reading a second bit data from the first bit is successful.

19. The method of claim 16 , wherein the examining whether the second bit of the memory array is functional comprises at least one of examining whether writing a third bit data to the second bit and examining whether reading a fourth bit data from the second bit is successful.

20. The method of claim 16 , wherein the plurality of assist circuits associated with the first bit comprises a first assist circuit coupled to the first bit through a first word line, and a second assist circuit coupled to the first bit through a first bit line, and wherein the plurality of assist circuits associated with the second bit comprises a third assist circuit coupled to the second bit through a second word line, and a fourth assist circuit coupled to the second bit through a second bit line.

Continuity (2)
Continuation 15291761 · Oct 12, 2016
Related Publication 20180102181A1 · Apr 12, 2018