Semiconductor devices
Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
1. A semiconductor device, comprising:
a substrate including an active region that extends in a first direction;
a plurality of bit line structures that run across the active region in a second direction crossing the first direction;
a first spacer on a sidewall of one or more of the bit line structures; and
a storage node contact on the active region between adjacent bit line structures,
the first spacer including,
a first part between the storage node contact and one or more of the bit line structures;
a second part between the first part and the storage node contact; and
a third part between the first part and the second part,
a minimum vertical thickness of the first part being greater than a maximum vertical thickness of the third part, and
the maximum vertical thickness of the third part being greater than a maximum vertical thickness of the second part.
2. The semiconductor device of claim 1 , wherein the first spacer comprises an insulation layer and an air gap surrounded by the insulation layer.
3. The semiconductor device of claim 1 , wherein the first part includes a first insulation layer, the second part includes a second insulation layer, and the third part includes a third insulation layer and an air gap surrounded by the third insulation layer,
wherein the first to third insulation layers have substantially the same material.
4. The semiconductor device of claim 1 , wherein a minimum vertical thickness of the third part is substantially the same as the maximum vertical thickness of the second part.
5. The semiconductor device of claim 1 , wherein the third part comprises an upper portion exposed from the first and second parts, the upper portion having an angulated corner.
6. The semiconductor device of claim 1 , wherein the third part comprises an upper portion exposed from the first and second parts, the upper portion having a rounded corner.
7. The semiconductor device of claim 1 , further comprising a second spacer on opposite sidewall of one or more of the bit line structures and facing each other with the storage node contact therebetween,
wherein the second spacer includes,
a first part between the storage node contact and one or more of the bit line structures; and
a second part between the storage node contact and the first part of the second spacer,
wherein a minimum vertical thickness of the first part of the second spacer is greater than a maximum vertical thickness of the second part of the second spacer.
8. The semiconductor device of claim 7 , wherein a maximum vertical thickness of the first part of the second spacer is substantially the same as the minimum vertical thickness of the first part of the second spacer.
9. The semiconductor device of claim 7 , wherein the maximum vertical thickness of the second part of the second spacer is substantially the same as a minimum vertical thickness of the second part of the second spacer.
10. The semiconductor device of claim 1 , wherein the second part has a top surface that is higher than a top surface of the storage node contact.
11. The semiconductor device of claim 1 , further comprising a landing pad on the storage node contact,
wherein the landing pad is in contact with a top surface of the first part, a top surface of the second part, and a top surface of the third part.
12. A semiconductor device, comprising:
a substrate including an active region that extends in a first direction;
a plurality of bit line structures that run across the active region in a second direction crossing the first direction;
a first spacer on a sidewall of one or more of the bit line structures; and
a storage node contact on the active region between adjacent bit line structures,
the first spacer including,
a first part between the storage node contact and one or more of the bit line structures;
a second part between the first part and the storage node contact, the second part having a top surface that is lower than a top surface of the first part; and
a third part between the first part and the second part,
the third part including an insulation layer and an air gap surrounded by the insulation layer, the air gap having a top surface positioned between the top surface of the first part and the top surface of the second part.
13. The semiconductor device of claim 12 , wherein the third part has a top surface positioned between the top surface of the first part and the top surface of the second part.
14. The semiconductor device of claim 13 , wherein the top surface of the first part, the top surface of the second part, and the top surface of the third part are exposed from the storage node contact.
15. The semiconductor device of claim 13 , further comprising a landing pad on the storage node contact,
wherein the landing pad is in contact with the top surface of the first part, the top surface of the second part, and the top surface of the third part.