Method and device for electrical current delivery using parallel semiconductor switches
The disclosure relates to a method and a control device for controlling at power semiconductor switches connected in parallel for switching a total current. The semiconductor switches each have a gate terminal. An input terminal for feeding the total current, an output terminal for discharging the total current, and a joint control terminal for receiving a joint control signal that has the state ‘disconnect’ or ‘connect’ are provided. The power semiconductor switches are each connected between to the input terminal and the output terminal. At least one ascertainment unit is designed to receive the joint control signal, ascertain individual control signals in accordance with the joint control signal to control the individual power semiconductor switches, and output the individual control signals to the gate terminals of the power semiconductor switches. The individual control signals each have the state ‘disconnect’ or ‘connect’ and differ at least temporarily.
1. A method for controlling at least two power semiconductor switches connected in parallel for switching a total current, the at least two power semiconductor switches each having a gate terminal configured to control the respective power semiconductor switch, the method comprising:
providing (i) an input terminal configured to feed the total current, (ii) an output terminal configured to conduct away the total current, and (iii) a common control terminal configured to receive a common control signal, the common control signal having an open state and a close state, the at least two power semiconductor switches each being connected to the input terminal on an input side of the respective power semiconductor switch and to the output terminal on an output side of the respective power semiconductor switch;
receiving, with an input side of at least one ascertaining unit, the common control signal;
determining a loading of each of the at least two power semiconductor switches;
ascertaining, with the at least one ascertaining unit, at least two individual control signals configured to control the at least two power semiconductor switches based on the common control signal, the at least two individual control signals each having the open state and the close state, the at least two individual control signals differing at least at times, wherein the ascertaining of each of the at least two individual control signals is based on the determined loading of the respective power semiconductor switch to be controlled; and
outputting, with an output side of the at least one ascertaining unit, the at least two individual control signals to the respective gate terminals of the at least two power semiconductor switches.
2. The method as claimed in claim 1 , the ascertaining further comprising:
ascertaining the at least two individual control signals such that, while the common control signal has the close state, at least one first of the at least two individual control signals has the open state.
3. The method as claimed in claim 2 , the ascertaining further comprising:
ascertaining the at least two individual control signals such that, while the common control signal has the open state, all of the at least two individual control signals have the open state and, while the common control signal subsequently has the close state, at least one second of the at least two individual control signal has the open state.
4. The method as claimed in claim 3 , the ascertaining further comprising:
ascertaining the at least two individual control signals such that, in a case of the common control signal having successive close states, alternately different individual control signals of the at least two individual control signals have the open state in an alternating manner.
5. The method as claimed in claim 1 , the ascertaining further comprising:
ascertaining the at least two individual control signals such that an individual control signal of the at least two individual control signals has the close state if the determined loading of the respective power semiconductor switch to be controlled is lower than a predefinable loading threshold value.
6. The method as claimed in claim 1 , the determining of the loading further comprising:
determining the loading of each of the at least two power semiconductor switches based on at least one of a temperature of the respective power semiconductor switch, a power loss of the respective power semiconductor switch, a transmitted quantity of energy of the respective power semiconductor switch, and a switching frequency of the respective power semiconductor switch.
7. The method as claimed in claim 1 , further comprising:
determining a functionality of each of the at least two power semiconductor switches,
wherein the ascertaining of each of the at least two individual control signals is such that an individual control signal of the at least two individual control signals has the close state if the respective power semiconductor switch to be controlled is determined to be functional.
8. The method as claimed in claim 1 , wherein at least partly parallel-connected power semiconductor modules are used as the at least two power semiconductor switches, each power semiconductor module including power semiconductor switches connected in parallel.
9. An electrical system for switching a total current comprising:
an input terminal configured to feed the total current;
an output terminal configured to conduct away the total current;
at least two power semiconductor switches connected in parallel, the at least two power semiconductor switches each having a gate terminal configured to control the respective power semiconductor switch, the at least two power semiconductor switches each being connected to the input terminal on an input side of the respective power semiconductor switch and to the output terminal on an output side of the respective power semiconductor switch;
a common control terminal configured to receive a common control signal, the common control signal having an open state and a close state; and
at least one ascertaining unit configured to:
receive the common control signal at an input side of the at least one ascertaining unit;
determine a functionality of each of the at least two power semiconductor switches;
ascertain at least two individual control signals configured to control the at least two power semiconductor switches based on the common control signal, the at least two individual control signals each having the open state and the close state, the at least two individual control signals differing at least at times, wherein the ascertainment of each of the at least two individual control signals is such that an individual control signal of the at least two individual control signals has the close state if the respective power semiconductor switch to be controlled is determined to be functional; and
output, with an output side of the at least one ascertaining unit, the at least two individual control signals to the respective gate terminals of the at least two power semiconductor switches.
10. The electrical system according to claim 9 , wherein the electrical system is within a vehicle.
11. A computer program stored in a non-transitory electronic storage medium for an electrical system having (i) an input terminal configured to feed a total current, (ii) an output terminal configured to conduct away the total current, (iii) at least two power semiconductor switches connected in parallel for switching the total current, the at least two power semiconductor switches each having a gate terminal configured to control the respective power semiconductor switch, the at least two power semiconductor switches each being connected to the input terminal on an input side of the respective power semiconductor switch and to the output terminal on an output side of the respective power semiconductor switch, and (iv) a common control terminal configured to receive a common control signal, the common control signal having an open state and a close state, the computer program being configured to, when executed, cause at least one ascertaining unit to:
receive, with an input side of the at least one ascertaining unit, the common control signal;
determine a loading of each of the at least two power semiconductor switches;
ascertain at least two individual control signals configured to control the at least two power semiconductor switches based on the common control signal, the at least two individual control signals each having the open state and the close state, the at least two individual control signals differing at least at times, wherein the ascertainment of each of the at least two individual control signals is based on the determined loading of the respective power semiconductor switch to be controlled; and
output, with an output side of the at least one ascertaining unit, the at least two individual control signals to the respective gate terminals of the at least two power semiconductor switches.