Methods and systems for sharing information between processors
Methods and systems for sharing access to a computer resource accessible by a bus between two controllers are provided. For example, a machine implemented method of sharing access to computer resources includes requesting access to a bus from a processor of a first controller to access a device shared with a processor of a second controller; waiting for a positive response from the second controller; when the positive response is received, accessing the bus for less than a first timeout period; resetting a timer before the timer reaches the first timeout period to extend access to the bus, when access is not complete and a total access time is less than a second timeout period; and releasing the bus when access is complete or the second timeout period has been reached.
1. A method comprising:
requesting, by a first processor of a first computing device, access to a bus attached to a device, wherein the bus and device are shared by the first computing device and a second computing device;
waiting, by the first processor of the first computing device, for a positive response from the second computing device for the requested access to the bus;
accessing, by the first processor of the first computing device, the bus for less than a first timeout period when the positive response is received;
resetting, by the first processor of the first computing device, a timer before the timer reaches the first timeout period to extend access to the bus, when access is not complete and a total access time is less than a second timeout period, wherein the first timeout period is different from the second timeout period; and
releasing, by the first processor of the first computing device, the bus when access is complete or the second timeout period has been reached.
2. The method of claim 1 , wherein the bus is an inter-integrated circuit (I2C) bus.
3. The method of claim 1 , further comprising:
tracking, by the first processor of the first computing device, an indication of a state of the bus, wherein the state comprises at least one of: inactive, waiting, local active, and remote active.
4. The method of claim 3 , wherein requesting access to a bus occurs when the indication indicates the bus is in an inactive state.
5. The method of claim 3 , further comprising:
updating, by the first processor of the first computing device, the indication of the state of the bus to represent waiting, when requesting access to a bus; and
updating, by the first processor of the first computing device, the indication of the state of the bus to represent local active when the positive response is received.
6. A non-transitory, machine readable storage medium having stored thereon instructions for performing a method, comprising machine executable code which when executed by at least one machine, causes the machine to:
request access to a bus attached to a device, wherein the bus and device are shared by a first computing device and a second computing device;
wait for a positive response from the second computing device for the requested access to the bus;
access the bus for less than a first timeout period when the positive response is received;
reset a timer before the timer reaches the first timeout period to extend access to the bus, when access is not complete and a total access time is less than a second timeout period, wherein the first timeout period is different to the second timeout period; and
release the bus when access is complete or the second timeout period has been reached.
7. The storage medium of claim 6 , wherein the bus is an I2C bus.
8. The storage medium of claim 6 , further comprises track an indication of the state of the bus, wherein the state comprises at least one of: inactive, waiting, local active, and remote active.
9. The storage medium of claim 8 , wherein requesting access to a bus occurs when the indication indicates the bus is in an inactive state.
10. The method of claim 8 , further comprises:
update the indication of the state of the bus to represent waiting, when requesting access to a bus; and
update the indication of the state of the bus to represent local active when the positive response is received.
11. A computing device comprising:
a processor;
a memory coupled to the processor which is configured to be capable of executing programmed instructions comprising and stored in the memory to:
request access to a bus attached to a device, wherein the bus and device are shared by a first computing device and a second computing device;
wait for a positive response from the second computing device for the requested access to the bus;
access the bus for less than a first timeout period when the positive response is received;
reset a timer before the timer reaches the first timeout period to extend access to the bus, when access is not complete and a total access time is less than a second timeout period, wherein the first timeout period is different to the second timeout period; and
release the bus when access is complete or the second timeout period has been reached.
12. The device as set forth in claim 11 wherein the bus is an I2C bus.
13. The device as set forth in claim 12 , wherein requesting access to a bus occurs when the indication indicates the bus is in an inactive state.
14. The device as set forth in claim 12 wherein the processor coupled to the memory is further configured to be capable of executing at least one additional programmed instruction comprising and stored in the memory to:
update the indication of the state of the bus to represent waiting, when requesting access to a bus; and
update the indication of the state of the bus to represent local active when the positive response is received.
15. The device as set forth in claim 11 wherein the processor coupled to the memory is further configured to be capable of executing at least one additional programmed instruction comprising and stored in the memory to track an indication of the state of the bus, wherein the state comprises at least one of: inactive, waiting, local active, and remote active.