LDMOS transistor and fabrication method thereof
Lateral double-diffused MOSFET transistor and fabrication method thereof are provided. A shallow trench isolation structure is formed in a semiconductor substrate. A drift region is formed in the semiconductor substrate and surrounding the shallow trench isolation structure. A body region is formed in the semiconductor substrate and distanced from the drift region. A gate structure is formed on a portion of each of the body region, the drift region, and the shallow trench isolation structure. A drain region is formed in the drift region on one side of the gate structure. A source region is formed in the body region on an other side of the gate structure. A first shallow doped region is formed in the drain region and the drift region to surround the shallow trench isolation structure.
1. A method of forming a lateral double-diffused MOSFET (LDMOS) transistor, comprising:
forming a shallow trench isolation structure in a semiconductor substrate;
forming a drift region in the semiconductor substrate, the drift region surrounding the shallow trench isolation structure;
forming a body region in the semiconductor substrate and distanced from the drift region;
forming a gate structure on a portion of each of the body region, the drift region, and the shallow trench isolation structure;
forming a drain region in the drift region on one side of the gate structure;
forming a source region in the body region on another side of the gate structure;
forming a first shallow doped region in the drain region and the drift region to surround the shallow trench isolation structure, the first shallow doped region having a same doping type as for the drain region and a depth less than the drain region and the drift region; and
forming a second doped region in the source region simultaneously when forming the first shallow doped region, wherein
the second doped region has a first distance away from an adjacent side of the gate structure and a depth of the second doped region is less than a depth of the source region, and
the second doped region has a same doping type as that of the source region.
2. The method according to claim 1 , further including:
performing a single-angle ion implantation process for forming the first shallow doped region without rotating the semiconductor substrate, the single-angle ion implantation process injecting ions in a direction from the drain region toward the source region with a first angle between an implanted ion incident direction and a normal to a surface of the semiconductor substrate.
3. The method according to claim 2 , wherein:
the first shallow doped region has a depth of approximately 10 nm˜50 nm and an ion doping concentration of approximately 1E18 atom/cm 3 to 1E19 atom/cm 3 .
4. The method according to claim 1 , wherein:
the LDMOS transistor is a P-type LDMOS transistor;
the doping type of the body region is N-type;
the doping type of the drift region is P-type;
the doping type of the drain region is P-type;
the doping type of the first shallow doped region is P-type; and
the doping type of the source region is P-type.
5. The method according to claim 4 , wherein:
BF 2 ions or B ions are implanted to form the first shallow doped region using a single-angle ion implantation process.
6. The method according to claim 5 , further including:
employing an implantation angle of approximately 15° to 40°, an implantation dose of approximately 1E13 atoms/cm 2 to 1E14 atoms/cm 2 , and an implantation energy of approximately 5 Kev to 40 Kev for implanting BF 2 ions or B ions.
7. A method of forming a lateral double-diffused MOSFET (LDMOS) transistor, comprising:
forming a shallow trench isolation structure in a semiconductor substrate;
forming a drift region in the semiconductor substrate, the drift region surrounding the shallow trench isolation structure;
forming a body region in the semiconductor substrate and distanced from the drift region;
forming a gate structure on a portion of each of the body region, the drift region, and the shallow trench isolation structure;
forming a drain region in the drift region on one side of the gate structure;
forming a source region in the body region on another side of the gate structure; and
forming a first shallow doped region in the drain region and the drift region to surround the shallow trench isolation structure, the first shallow doped region having a same doping type as for the drain region and a depth less than the drain region and the drift region, wherein BF 2 ions or B ions are implanted to form the first shallow doped region using a single-angle ion implantation process, wherein
the LDMOS transistor is a P-type LDMOS transistor,
the doping type of the body region is N-type,
the doping type of the drift region is P-type,
the doping type of the drain region is P-type,
the doping type of the first shallow doped region is P-type,
the doping type of the source region is P-type, and
implanting diffusion-preventing ions during the single-angle ion implantation process, wherein the diffusion-preventing ions include C ions or N ions.
8. The method according to claim 7 , further including:
employing an implantation angle of approximately 15° to 40°, an implantation dose of approximately 5E12 atoms/cm 2 to 5E15 atoms/cm 2 , and an implantation energy of approximately 0.5 Kev to 20 Kev for implanting C ions or N ions.
9. The method according to claim 4 , wherein:
a source-drain ion implantation process is performed for forming the source region and the drain region, the source-drain ion implantation process implanting one or more of B ions, BF 2 ions, Ga ions and In ions with an implantation angle of approximately 0°-5°, an implantation dose of approximately 5E13 atoms/cm 2 to 5E15 atoms/cm 2 , and an implantation energy of approximately 6 Kev to 50 Kev.
10. The method according to claim 1 , wherein:
the LDMOS transistor is an N-type LDMOS transistor;
the doping type of the body region is P-type;
the doping type of the drift region is N-type;
the doping type of the drain region is N-type;
the doping type of the first shallow doped region is N-type; and
the doping type of the source region is N-type.
11. The method according to claim 10 , wherein:
P ions or As ions are implanted to form the first shallow doped region using a single-angle ion implantation process.
12. The method according to claim 11 , further including:
employing an implantation angle of approximately 15° to 40°, an implantation dose of approximately 1E13 atoms/cm 2 to 1E14 atoms/cm 2 , and an implantation energy of approximately 8 Kev to 45 Kev for implanting P ions or As ions.
13. The method according to claim 11 , further including:
implanting diffusion-preventing ions during the single-angle ion implantation process, wherein the diffusion-preventing ions include C ions or N ions.
14. The method according to claim 13 , further including:
employing an implantation angle of approximately 15° to 40°, an implantation dose of approximately 5E12 atoms/cm 2 to 5E15 atoms/cm 2 , and an implantation energy of approximately 0.5 Kev to 20 Kev for implanting C ions or N ions.
15. The method according to claim 10 , wherein:
a source-drain ion implantation process is performed in forming the source region and the drain region, the source-drain ion implantation process implanting one or more of P ions, As ions, and Sb ions with an implantation angle of approximately 0°˜5°, an implantation dose of approximately 5E13 atoms/cm 2 to 5E15 atoms/cm 2 , and an implantation energy of approximately 12 Kev to 50 Kev.
16. An LDMOS transistor, comprising:
a semiconductor substrate;
a shallow trench isolation structure in the semiconductor substrate;
a drift region located in the semiconductor substrate and surrounding the shallow trench isolation structure;
a body region located in the semiconductor substrate and distanced from the drift region;
a gate structure on a portion of each of the body region, the drift region, and the shallow trench isolation structure;
a drain region located in the drift region on one side of the gate structure;
a source region located in the body region on an other side of the gate structure; and
a first shallow doped region located in the drain region and in the drift region to surround the shallow trench isolation structure, the first shallow doped region having a same doping type as that of the drain region and a depth less than the drain region and the drift region, wherein
the first shallow doped region further includes diffusion-preventing ions, and
the diffusion-preventing ions include C ions or N ions.
17. The LDMOS transistor according to claim 16 , wherein:
the first shallow doped region has a depth of approximately 10 nm˜50 nm and an ion doping concentration of approximately 1E18 atom/cm 3 to 1E19 atom/cm 3 .
18. The LDMOS transistor according to claim 16 , further including:
a second doped region in the source region, wherein:
the second doped region has a first distance away from an adjacent side of the gate structure and has a depth less than the source region.
19. The method according to claim 7 , further including:
employing an implantation angle of approximately 15° to 40°, an implantation dose of approximately 1E13 atoms/cm 2 to 1E14 atoms/cm 2 , and an implantation energy of approximately 5 Kev to 40 Kev for implanting BF 2 ions or B ions.
20. The LDMOS transistor according to claim 16 , wherein:
the LDMOS transistor is an N-type LDMOS transistor;
the doping type of the body region is P-type;
the doping type of the drift region is N-type;
the doping type of the drain region is N-type;
the doping type of the first shallow doped region is N-type; and
the doping type of the source region is N-type.