IP Library › Granted Patent US 10,008,492
Granted Patent B2
US 10,008,492 · App. 15/353,348 · Granted Jun 26, 2018

Electrostatic discharge (ESD) protection device and method fabricating the ESD protection device

Inventors: Chung-Yu Huang (Tainan, TW); Ping-Chen Chang (Pingtung County, TW); Hou-Jen Chiu (Taichung, TW)
Assignee: United Microelectronics Corp.
H01L27/0285H01L29/0649H01L29/0847H01L29/1083H01L29/66575
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Quick Facts
Patent No.
US 10,008,492
App. No.
15/353,348
Granted
Jun 26, 2018
Kind
B2
Abstract

An electrostatic discharge (ESD) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. A first doped region of the first conductive type is disposed within the drain doped region and being at least distant from the gate structure by a distance. The first doped region has a second impurity concentration lower than the first impurity concentration.

Claims (29)

1. An electrostatic discharge (ESD) device, comprising:

a gate structure, disposed on a substrate;

a drain doped region of a first conductive type in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration; and

a first doped region of the first conductive type, disposed within the drain doped region and being at least distant from the gate structure by a distance, wherein the first doped region has a second impurity concentration lower than the first impurity concentration.

2. The ESD protection device of claim 1 , wherein the distance between the gate structure and the first doped region is in a range of 0.08 microns to 0.28 microns.

3. The ESD protection device of claim 1 , wherein the distance between the gate structure and the first doped region is in a range of 0.1 microns to 0.2 microns.

4. The ESD protection device of claim 1 , wherein the first doped region comprises an impurity of the first conductive type or a combination of impurities of two conductive types.

5. The ESD protection device of claim 1 , further comprising a first doped well of the first conductive type in the substrate under the drain doped region and the first doped region.

6. The ESD protection device of claim 5 , wherein the second impurity concentration of the first doped region is higher than, equal to, or lower than a third impurity concentration of the first doped well.

7. The ESD protection device of claim 5 , wherein a portion of the first doped well serves as the first doped region.

8. The ESD protection device of claim 1 , further comprising a source doped region of the first conductive type in the substrate, at a second side of the gate structure.

9. The ESD protection device of claim 8 , further comprising a second doped well of a second conductive type in the substrate under the source doped region, wherein the first conductive type to opposite to the second conductive type.

10. The ESD protection device of claim 9 , further comprising a second doped region of the second conductive type within the second doped well, wherein the second doped region is isolated from the source doped region by an isolation structure.

11. The ESD protection device of claim 9 , wherein the first doped well and the second doped well are in contact under the gate structure, or the first doped well and the second doped well have a separation under the gate structure.

12. A method for fabricating an electrostatic discharge (ESD) device, comprising:

providing a substrate;

forming a gate structure on the substrate;

forming a drain doped region of a first conductive type in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration; and

forming a first doped region of the first conductive type, within the drain doped region and being at least distant from the gate structure by a distance, wherein the first doped region has a second impurity concentration lower than the first impurity concentration.

13. The method for fabricating the ESD protection device of claim 12 , wherein the distance between the gate structure and the first doped region is in a range of 0.08 microns to 0.28 microns.

14. The method for fabricating the ESD protection device of claim 12 , wherein the distance between the gate structure and the first doped region is in a range of 0.1 microns to 0.2 microns.

15. The method for fabricating the ESD protection device of claim 12 , further comprising forming a first doped well of the first conductive type in the substrate under the drain doped region and the first doped region.

16. The method for fabricating the ESD protection device of claim 15 , wherein a portion of the first doped well serves as the first doped region.

17. The method for fabricating the ESD protection device of claim 12 , further comprising doping an impurity of the second conductive type into the drain doped region to form the first doped region.

18. The method for fabricating the ESD protection device of claim 12 , further comprising doping an impurity of the first conductive type into the drain doped region to form the first doped region wherein a doping concentration of the impurity of the first doped region is lower than a doping concentration of the impurity of the drain doped region.

19. The method for fabricating the ESD protection device of claim 12 , further comprising forming a source doped region of the first conductive type in the substrate, at a second side of the gate structure.

20. The method for fabricating the ESD protection device of claim 19 , further comprising forming a second doped well of a second conductive type in the substrate under the source doped region, wherein the first conductive type to opposite to the second conductive type.

21. The method for fabricating the ESD protection device of claim 20 , further comprising forming a second doped region of the second conductive type within the second doped well, wherein the second doped region is isolated from the source doped region by an isolation structure.

22. The method for fabricating the ESD protection device of claim 20 , wherein the first doped well and the second doped well are in contact under the gate structure, or the first doped well and the second doped well have a separation under the gate structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2016
From: HUANG, CHUNG-YU; CHANG, PING-CHEN; CHIU, HOU-JEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 040347/0232 →
Continuity (1)
Related Publication 20180138167A1 · May 17, 2018
Cited By (1)
US 12,237,323