FET including an InGaAs channel and method of enhancing performance of the FET

1. A method of manufacturing a FET device having a set BTBT leakage and a maximum V DD , the method comprising:

determining an x value in In x Ga 1-x As according to the BTBT leakage and the maximum V DD ; and

forming a channel utilizing In x Ga 1-x As, wherein x is not 0.53,

wherein the x value is determined to be lower than 0.5 for a BTBT of 0.1 nA/μm or lower, and the x value is determined to be greater than 0.53 for a BTBT of 10 nA/μm or greater.

2. The method of claim 1 , wherein the maximum V DD is 0.85 V, and x is 0.40 or less.

3. The method of claim 1 , wherein the device is an SLVT, and x is at least 0.60.

4. The method of claim 1 , wherein the device is a RVT device, and x is 0.40 or less.

5. A method of manufacturing a FET device having a first set BTBT leakage and a first maximum V DD , the method comprising:

determining a value of x in In x Ga 1-x As according to the first set BTBT leakage and the first maximum V DD ;

forming a first channel utilizing In x Ga 1-x As;

determining a second BTBT leakage for an LVT and/or SLVT device;

determining a value of y in In y Ga 1-y As according to the second BTBT leakage for the LVT and/or SLVT device; and

forming a second channel utilizing In y Ga 1-y As, wherein y is greater than x.

6. The method of claim 5 , wherein y≥x+0.1.

7. A FET device, comprising a first FET comprising a gate electrode, an In x Ga 1-x As channel, and a buffer layer between the gate electrode and the channel,

wherein x is not 0.53,

BTBT leakage is 0.1 nA/μm or lower, and

the FET device is configured to operate with a maximum V DD of at least 0.7 V,

wherein the FET device further comprises a second FET comprising a second channel comprising In y Ga 1-y As, wherein y is greater than x, and the second FET has a BTBT leakage of 1 nA/μm or lower.

8. The FET device of claim 7 , wherein x is about 0.3-0.4, and the FET device is configured to operate with the maximum V DD of at least 0.8 V.

9. The FET device of claim 7 , wherein x is about 0.2-0.3, and the FET device is configured to operate with the maximum V DD of at least 0.8 V.

10. The FET device of claim 7 , wherein the first FET further comprises a buffer layer between the gate electrode and the In x Ga 1-x As channel, the buffer layer comprising a compound selected from the group consisting of InGaP, InAlAs, and a combination thereof.

11. The FET device of claim 7 , further comprising a third FET comprising a third channel comprising In z Ga 1-z As, wherein z is greater than or equal to y, and the third FET has a BTBT leakage of 10 nA/μm or lower.

12. The FET device of claim 11 , wherein x<y<z.

13. The FET device of claim 11 , wherein 0.2≤x<y<z≤0.8.