IP Library Granted Patent US 10,008,920
Granted Patent B2
US 10,008,920 · App. 15/548,960 · Granted Jun 26, 2018

Apparatus and method of fast commutation for matrix converter-based rectifier

Inventors: Tao Zhao (Markham, CA); Dewei Xu (Markham, CA); Jahangir Afsharian (Markham, CA); Bing Gong (Markham, CA); Zhihua Yang (Markham, CA)
Assignee: MURATA MANUFACTURING CO., LTD.
H02M1/088H02M7/1552H02M7/1623
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Quick Facts
Patent No.
US 10,008,920
App. No.
15/548,960
Granted
Jun 26, 2018
Kind
B2
Abstract

A method of commutation in a matrix rectifier from an active vector to a zero vector includes two steps. A method of commutation in a matrix rectifier from a zero vector to an active vector includes three steps.

Claims (112)

1. A method of performing commutation in a matrix rectifier from an active vector to a zero vector, the matrix rectifier includes:

first, second, and third phases; and

uni-directional switches S ij , where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches S 1j and S 2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches; wherein

first ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node;

first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node;

second ends of the first and fourth bidirectional switches are connected to the first phase;

second ends of the third and sixth bidirectional switches are connected to the second phase;

second ends of the fifth and second bidirectional switches are connected to the third phase;

a zero vector is defined by either uni-directional switches S 1m and S 1n switched on or uni-directional switches S 2m and S 2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches S pq switched off, where p≠m and q≠n; and

an active vector is defined by either uni-directional switches S 1m and S 1n switched on or uni-directional switches S 2m and S 2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches S pq switched off, where p≠m and q≠n;

Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6);

the method comprising:

step (a):

for an active vector with uni-directional switches S 1m and S 1n switched on,

in Sectors I, III, V, turning on uni-directional switch S 1x , where x is chosen such that (m, x)=(1, 4), (3, 6), (5, 2); and

in Sectors II, IV, VI, turning on uni-directional switch S 1x , where x is chosen such that (x, n)=(1, 4), (3, 6), (5, 2); or

for an active vector with uni-directional switches S 2m and S 2n switched on,

in Sectors I, III, V, turning on uni-directional switch S 2y , where y is chosen such that (y, n)=(1, 4), (3, 6), (5, 2); and

in Sectors II, IV, VI, turning on uni-directional switch S 2y , where y is chosen such that (m, y)=(1, 4), (3, 6), (5, 2);

step (b):

for the active vector with uni-directional switches S 1m and S 1n initially switched on,

in Sectors I, III, V, turning off uni-directional switch S 1n ; and

in Sectors II, IV, VI, turning off uni-directional switch S 1m ; or

for the active vector with uni-directional switches S 2m and S 2n initially switched on,

in Sectors I, III, V, turning off uni-directional switch S 2m ;

in Sectors II, IV, VI, turning off uni-directional switch S 2n .

2. The method of claim 1 , wherein commutation is performed by measuring input voltage and without measuring output current or output voltage.

3. A method of operating a matrix rectifier comprising:

performing commutation from an active vector to a zero vector using the method of claim 1 ; and

modulating the first, second, third, fourth, fifth, and sixth bi-directional switches based on space vector modulation.

4. The method of claim 3 , wherein gate signals s ij applied to uni-directional switches S ij are generated by:

determining a space-vector-modulation sector; and

generating:

a carrier signal;

first, second, and third comparison signals based on dwell times of corresponding zero vector and two active vectors of the space-vector-modulation sector;

modulation signals s j corresponding to the first, second, third, fourth, fifth, and sixth bi-directional switches based on the comparison of the carrier signal and the first, second, and third comparison signals, where j=1, 2, 3, 4, 5, 6;

first converter select signal SelectCon1 and second converter select signal SelectCon2 based on if a positive or a negative voltage is outputted; wherein

the gate signals s ij are generated based on:

s 1j =s j ×SelectCon1( j= 1,3,5,4,6,2)

s 2j =s j ×SelectCon2( j= 1,3,5,4,6,2).

5. A method of performing commutation in a matrix rectifier from a zero vector to an active vector, the matrix rectifier includes:

first, second, and third phases; and

uni-directional switches S ij , where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches S 1j and S 2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches; wherein

first ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node;

first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node;

second ends of the first and fourth bidirectional switches are connected to the first phase;

second ends of the third and sixth bidirectional switches are connected to the second phase;

second ends of the fifth and second bidirectional switches are connected to the third phase;

a zero vector is defined by either uni-directional switches S 1m and S 1n switched on or uni-directional switches S 2m and S 2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches S pq switched off, where p≠m and q≠n;

an active vector is defined by either uni-directional switches S 1m and S 1n switched on or uni-directional switches S 2m and S 2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches S pq switched off, where p≠m and q≠n; and

Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6);

the method comprising:

step (a):

for a zero vector with uni-directional switches S 1m and S 1n switched on,

in Sectors I, III, V, turning on uni-directional switch S 1x , where x=1, 3, 5 and x is chosen such that a negative voltage is provided at the positive-voltage node; and

in Sectors II, IV, VI, turning on uni-directional switch S 1x , where x=2, 4, 6 and x is chosen such that a positive voltage is provided at the negative-voltage node; or

for a zero vector with uni-directional switches S 2m and S 2n switched on,

in Sectors I, III, V, turning on uni-directional switch S 2y , where y=2, 4, 6 and y is chosen such that a positive voltage is provided at the negative-voltage node; and

in Sectors II, IV, VI, turning on uni-directional switch S 2y , where y=1, 3, 5 and y is chosen such that a negative voltage is provided at the positive-voltage node;

step (b):

for the zero vector with uni-directional switches S 1m and S 1n initially switched on,

in Sectors I, III, V, turning off uni-directional switch S 1m ; and

in Sectors II, IV, VI, turning off uni-directional switch S 1n ; or

for the zero vector with uni-directional switches S 2m and S 2n initially switched on,

in Sectors I, III, V, turning off uni-directional switch S 2n ; and

in Sectors II, IV, VI, turning off uni-directional switch S 2m ; and

step (c):

for the zero vector with uni-directional switches S 1m and S 1n initially switched on,

in Sectors I, III, V, turning off uni-directional switches S 1x and S 1n and turning on uni-directional switches S 2x and S 2n ; and

in Sectors II, IV, VI, turning off uni-directional switches S 1x and S 1m and turning on uni-directional switches S 2x and S 2m ; or

for the zero vector with uni-directional switches S 2m and S 2n initially switched on,

in Sectors I, III, V, turning off uni-directional switches S 2m and S 2y and turning on uni-directional switches S 1m and S 1y ; and

in Sectors II, IV, VI, turning off uni-directional switches S 2n and S 2y and turning on uni-directional switches S 1n and S 1y .

6. The method of claim 5 , wherein commutation is performed by measuring input voltage and without measuring output current or output voltage.

7. The method of claim 5 , wherein in step (a):

for the zero vector with uni-directional switches S 1m and S 1n initially switched on, no current passes through uni-directional switch S 1x ; or

for the zero vector with uni-directional switches S 2m and S 2n initially switched on, no current passes through uni-directional switch S 2y .

8. The method of claim 5 , wherein step (b) lasts until a current through the positive-voltage node or the negative-voltage node reaches zero.

9. The method of claim 5 , further comprising a transformer connected to the positive-voltage and negative-voltage nodes; wherein

a holding time Δt of step (b) is provided by:

Δ

t

=

L

O

I

1

max

U

1

min

where I 1max is a maximum current of the matrix converter, U 1min is a minimum output voltage of the matrix converter, and L o is a leakage inductance of the transformer.

10. A method of operating a matrix rectifier comprising:

performing commutation from a zero vector to an active vector using the method of claim 5 ; and

modulating the first, second, third, fourth, fifth, and sixth bi-directional switches based on space vector modulation.

11. The method of claim 10 , wherein gate signals s ij applied to uni-directional switches S − ij are generated by:

determining a space-vector-modulation sector;

generating:

a carrier signal;

first, second, and third comparison signals based on dwell times of corresponding zero vector and two active vectors of the space-vector-modulation sector;

modulation signals s j corresponding to the first, second, third, fourth, fifth, and sixth bi-directional switches based on the comparison of the carrier signal and the first, second, and third comparison signals, where j=1, 2, 3, 4, 5, 6; and

first converter select signal SelectCon1 and second converter select signal SelectCon2 based on if a positive or a negative voltage is outputted; wherein

the gate signals s ij are generated based on:

s 1j =s j ×SelectCon1( j= 1,3,5,4,6,2)

s 2j =s j ×SelectCon2( j= 1,3,5,4,6,2).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2017
From: ZHAO, TAO; XU, DEWEI; AFSHARIAN, JAHANGIR; GONG, BING; YANG, ZHIHUA
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 043455/0304 →
Continuity (2)
Provisional Application 62138039 · Mar 25, 2015
Related Publication 20180076705A1 · Mar 15, 2018