Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus
The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.
1. A method comprising:
receiving data to transmit on a shared bus, wherein a plurality of memory chips and a plurality of dynamic resistors are coupled to the shared bus, wherein each of the plurality of dynamic resistors is assigned to a respective one of the plurality of memory chips;
evaluating the received data to identify at least one target chip of the plurality of memory chips, wherein the target chip is an intended recipient of the received data;
adjusting, based upon a location of the target chip on the shared bus, a resistance value of a dynamic resistor of the plurality of dynamic resistors coupled to the shared bus by transmitting a control signal on a communication link coupled to the dynamic resistor, the control signal providing the resistance value to the dynamic resistor, wherein the dynamic resistor is coupled to the shared bus at a location closest to the location of the target chip on the shared bus relative to where the other dynamic resistors couple to the shared bus, and wherein the communication link is separate from the shared bus; and
transmitting the received data on the shared bus using a driver while the dynamic resistor is at the adjusted resistance value.
2. A method comprising:
receiving data to transmit on a shared bus, wherein a plurality of memory chips and a plurality of dynamic resistors are coupled to the shared bus, wherein each of the plurality of dynamic resistors is assigned to a respective one of the plurality of memory chips;
evaluating the received data to identify at least one target chip of the plurality of memory chips, wherein the target chip is an intended recipient of the received data;
adjusting, based upon a location of the target chip on the shared bus, a resistance value of a dynamic resistor of the plurality of dynamic resistors coupled to the shared bus, wherein the dynamic resistor is coupled to the shared bus at a location closest to the location of the target chip on the shared bus relative to where the other dynamic resistors couple to the shared bus; and
transmitting the received data on the shared bus using a driver while the dynamic resistor is at the adjusted resistance value,
wherein the plurality of memory chips and dynamic resistors are coupled at different locations to the shared bus such that respective distances between the plurality of memory chips and the driver, and between the dynamics resistors and the driver, along the shared bus are different.
3. The method of claim 1 , wherein each of the plurality of memory chips comprises a DRAM memory module configured to store the received data transmitted on the shared bus.
4. A method comprising:
receiving data to transmit on a shared bus, wherein a plurality of memory chips and a plurality of dynamic resistors are coupled to the shared bus, wherein each of the plurality of dynamic resistors is assigned to a respective one of the plurality of memory chips;
evaluating the received data to identify at least one target chip of the plurality of memory chips, wherein the target chip is an intended recipient of the received data;
adjusting, based upon a location of the target chip on the shared bus, a resistance value of a dynamic resistor of the plurality of dynamic resistors coupled to the shared bus, wherein the dynamic resistor is coupled to the shared bus at a location closest to the location of the target chip on the shared bus relative to where the other dynamic resistors couple to the shared bus;
transmitting the received data on the shared bus using a driver while the dynamic resistor is at the adjusted resistance value; and
adjusting a respective resistance value of each of the plurality of dynamic resistors based upon the location of the target chip on the shared bus, wherein each of the respective resistance values is changed.
5. The method of claim 1 , wherein at least one of the plurality of dynamic resistors is a termination resistor coupled to a first end of the shared bus, wherein the driver is coupled to a second end of the bus opposite the first end.
6. The method of claim 1 , further comprising:
evaluating the received data to identify at least one non-target chip of the plurality of memory chips; and
deactivating the non-target chip before transmitting the received data on the shared bus using the driver.
7. The method of claim 1 , wherein the at least one target chip of the plurality of memory chips does not include all of the plurality of memory chips coupled to the shared bus.
8. The method of claim 1 , wherein the plurality of memory chips and dynamic resistors are coupled at different locations to the shared bus such that respective distances between the plurality of memory chips and the driver, and between the dynamics resistors and the driver, along the shared bus are different.
9. The method of claim 1 , further comprising:
adjusting a respective resistance value of each of the plurality of dynamic resistors based upon the location of the target chip on the shared bus, wherein each of the respective resistance values is changed.
10. The method of claim 1 , further comprising:
evaluating the received data to identify at least one non-target chip of the plurality of memory chips; and
deactivating the non-target chip before transmitting the received data on the shared bus using the driver.
11. The method of claim 2 , wherein each of the plurality of memory chips comprises a DRAM memory module configured to store the received data transmitted on the shared bus.
12. The method of claim 2 , further comprising:
adjusting a respective resistance value of each of the plurality of dynamic resistors based upon the location of the target chip on the shared bus, wherein each of the respective resistance values is changed.
13. The method of claim 2 , wherein at least one of the plurality of dynamic resistors is a termination resistor coupled to a first end of the shared bus, wherein the driver is coupled to a second end of the bus opposite the first end.
14. The method of claim 2 , further comprising:
evaluating the received data to identify at least one non-target chip of the plurality of memory chips; and
deactivating the non-target chip before transmitting the received data on the shared bus using the driver.
15. The method of claim 2 , wherein the at least one target chip of the plurality of memory chips does not include all of the plurality of memory chips coupled to the shared bus.
16. The method of claim 4 , wherein each of the plurality of memory chips comprises a DRAM memory module configured to store the received data transmitted on the shared bus.
17. The method of claim 4 , wherein at least one of the plurality of dynamic resistors is a termination resistor coupled to a first end of the shared bus, wherein the driver is coupled to a second end of the bus opposite the first end.
18. The method of claim 4 , further comprising:
evaluating the received data to identify at least one non-target chip of the plurality of memory chips; and
deactivating the non-target chip before transmitting the received data on the shared bus using the driver.
19. The method of claim 4 , wherein the at least one target chip of the plurality of memory chips does not include all of the plurality of memory chips coupled to the shared bus.