System-on-chip including asynchronous interface and driving method thereof
A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.
1. A system-on-chip (SoC), comprising:
a master;
a slave; and
an asynchronous interface having a first-in first-out (FIFO) memory connected to the master and the slave, wherein a write operation of the FIFO memory is controlled based on a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based on a comparison of a read pointer and an expected read pointer of the FIFO memory,
wherein the asynchronous interface is configured to keep an interval between the read pointer and the write pointer constant, and wherein the expected read pointer is calculated based on the write pointer and the interval, and the expected write pointer is calculated based on the read pointer and the interval.
2. The system-on-chip of claim 1 , wherein the FIFO memory comprises a first FIFO and a second FIFO, and the asynchronous interface comprises a slave interface and a master interface,
wherein the slave interface comprises a slave transmitter, a slave receiver, and a slave clock domain crossing (CDC) block having the first FIFO, and
wherein the master interface comprises a master transmitter, a master receiver, and a master clock domain crossing (CDC) block having the second FIFO connected to the master and the slave.
3. The system-on-chip of claim 1 , wherein the asynchronous interface is configured to transmit data to the FIFO memory in synchronization with a gated clock generated based on a master operation clock and a slave operation clock.
4. The system-on-chip of claim 1 , wherein a period of compensating an interval for the read operation of the FIFO memory is determined by a most significant bit (MSB) of the write pointer, and a period of compensating an interval for the write operation of the FIFO memory is determined by a most significant bit (MSB) of the write pointer.
5. The system-on-chip of claim 2 , wherein the asynchronous interface is configured to generate a write enable signal to control the write operation of the FIFO memory based on a result of the comparison of the write pointer and the expected write pointer.
6. The system-on-chip of claim 2 , wherein the asynchronous interface is configured to generate a read enable signal to control the read operation of the FIFO memory based on a result of the comparison of the read pointer and the expected read pointer.
7. The system-on-chip of claim 5 , wherein the FIFO memory is configured to store data at an address pointed by the write pointer when the write enable signal is activated.
8. The system-on-chip of claim 6 , wherein the FIFO memory is configured to transmit data stored at an address pointed by the read pointer to the master receiver or the slave receiver when the read enable signal is activated.
9. A method of operating a system-on-chip including a master, a slave and an asynchronous interface therebetween, the method comprising:
calculating an expected write pointer based on a write pointer, and a predefined interval between the write pointer and a read pointer of a FIFO memory in the asynchronous interface;
comparing the expected write pointer and the write pointer; and
controlling a write operation of the FIFO memory based on a result of the comparing the expected write pointer and the write pointer.
10. The method of claim 9 , wherein the FIFO memory comprises a first FIFO and a second FIFO, and the asynchronous interface comprises a slave interface and a master interface,
wherein the slave interface comprises a slave transmitter, a slave receiver, and a slave clock domain crossing (CDC) block having the first FIFO, and
the master interface comprises a master transmitter, a master receiver, and a master clock domain crossing (CDC) block having the second FIFO connected to the master and the slave.
11. The method of claim 10 , further comprising:
calculating an expected read pointer based on the read pointer and the predefined interval between the write pointer and the read pointer of the FIFO memory in the asynchronous interface;
comparing the expected read pointer and the read pointer; and
controlling a read operation of the FIFO memory based on a result of the comparing the expected read pointer and the read pointer.
12. The method of claim 10 , wherein the controlling the write operation of the FIFO memory comprises:
generating a write enable signal to control the write operation of the FIFO memory based on the result of the comparing the expected write pointer and the write pointer; and
storing data at an address pointed by the write pointer when the write enable signal is activated.
13. The method of claim 11 , wherein the controlling the read operation of the FIFO memory comprises:
generating a read enable signal to control the read operation of the FIFO memory based on the result of the comparing the expected read pointer and the read pointer; and
transmitting data stored at an address pointed by the read pointer to the master receiver or the slave receiver when the read enable signal is activated.
14. A method of operating a system-on-chip including a master, a slave and an asynchronous interface therebetween, the method comprising:
calculating an expected write pointer based on a write pointer, and a predefined interval between the write pointer and a read pointer of a FIFO memory in the asynchronous interface;
comparing the expected write pointer and the write pointer;
controlling a write operation of the FIFO memory based on a result of the comparing the expected write pointer and the write pointer;
calculating an expected read pointer based on the read pointer, and the predefined interval between the write pointer and the read pointer of the FIFO memory in the asynchronous interface;
comparing the expected read pointer and the read pointer; and
controlling a read operation of the FIFO memory based on a result of the comparing the expected read pointer and the read pointer.
15. The method of claim 14 , wherein the controlling the write operation of the FIFO memory comprises:
generating a write enable signal to control the write operation of the FIFO memory based on the result of the comparing the expected write pointer and the write pointer; and
storing data at an address pointed by the write pointer when the write enable signal is activated.
16. The method of claim 14 , wherein the controlling the read operation of the FIFO memory comprises:
generating a read enable signal to control the read operation of the FIFO memory based on a result of the comparing the expected read pointer and the read pointer; and
transmitting data stored at an address pointed by the read pointer to a receiver in the master or a receiver in the slave when the read enable signal is activated.
17. The method of claim 14 , further comprising keeping the predefined interval between the read pointer and the write pointer constant.
18. The method of claim 14 , wherein a period of compensating an interval for the read operation of the FIFO memory is determined by a most significant bit (MSB) of the write pointer, and a period of compensating an interval for the write operation of the FIFO memory is determined by a most significant bit (MSB) of the write pointer.