Providing access from outside a multicore processor SoC to individually configure voltages
Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.
1. An apparatus, comprising:
a multicore processor SoC (system-on-chip) including:
a communication interface to provide access from outside the multicore processor SoC based on a message interface protocol;
a plurality of cores;
a first memory that stores a plurality of embedded values correspondingly associated with the plurality of cores, each embedded value to indicate a default voltage for a respective one of the plurality of cores;
a power control unit (PCU); and
a second memory having instructions stored thereon that, in response to execution by the PCU, cause the PCU to perform operations to:
recognize, based on the message interface protocol, a value from a signal received over the communication interface, wherein the signal comprises a voltage request generated outside the multicore processor SoC to individually set a voltage of a core of the plurality of cores differently than a corresponding one of the default voltages;
control a voltage regulator associated with the multicore processor SoC responsive to the value recognized based on the message interface protocol to individually set the voltage of the core differently than the corresponding one of the default voltages.
2. The apparatus of claim 1 , wherein the voltage regulator comprises a fully integrated voltage regulator.
3. The apparatus of claim 1 , wherein the voltage regulator comprises an external voltage regulator coupled to the multicore processor SoC.
4. The apparatus of claim 3 , wherein the signal is delivered over at least one pin of a plurality of pins, wherein each pin of the plurality of pins corresponds to a respective core of the plurality of cores.
5. The apparatus of claim 1 , wherein a magnitude of the voltage of the core is different than a magnitude of the corresponding one of the default voltages.
6. The apparatus of claim 5 , wherein the value recognized based on the message interface protocol includes at least one of an actual voltage value, an offset from the corresponding one of the default voltages, or a base voltage value and an offset from the base voltage value.
7. The apparatus of claim 1 , wherein the value recognized based on the message interface protocol comprises a user selected value.
8. The apparatus of claim 1 , wherein the signal is from an OC (overclocking) Mailbox.
9. The apparatus of claim 1 , wherein the signal comprises information stored in a control register.
10. The apparatus of claim 1 , further comprising a Basic Input Output System (BIOS) to facilitate a user to generate the voltage request.
11. A non-transitory computer-readable medium having instructions stored thereon that, in response to execution by a power control unit (PCU) of a multicore processor SoC (system-on-chip) having an externally configurable interface, cause the PCU to perform operations, to:
recognize, based on a message interface protocol, a value from a signal received over the externally configurable interface, wherein the signal comprises a voltage request generated outside the multicore processor SoC to individually set a voltage of a core of a plurality of cores of the multicore processor SoC differently than a default voltage for the core; and
control a voltage regulator associated with the multicore processor SoC responsive to the value recognized based on the message interface protocol to individually set the voltage of the core differently than the default voltage.
12. The non-transitory computer-readable medium of claim 11 , wherein a magnitude of the voltage of the core is different than a magnitude of the default voltage.
13. The non-transitory computer-readable medium of claim 11 , wherein the value recognized based on the message interface protocol includes at least one of an actual voltage value, an offset from the default voltage, or a base voltage value and an offset from the base voltage value.
14. The non-transitory computer-readable medium of claim 11 , wherein the value recognized based on the message interface protocol comprises a user selected value.
15. The non-transitory computer-readable medium of claim 11 , wherein the signal is from an OC (overclocking) Mailbox.
16. A method, comprising:
identifying, by a power control unit (PCU) of a multicore processor system-on-chip (SoC) having an externally configurable interface, a message interface protocol to interpret voltage requests generated externally from the multicore processor SoC to individually set voltages of a plurality of cores of the multicore processor SoC to values that are different than values of default voltages correspondingly associated with the cores of the multicore processor SoC;
recognizing, by the PCU and based on the message interface protocol, a value from a signal received over the externally configurable interface, wherein the signal includes one of the voltage requests;
controlling, by the PCU, a voltage regulator associated with the multicore processor SoC responsive to the value recognized based on the message interface protocol to individually set one of the voltages differently than a corresponding one of the default voltages.
17. The method of claim 16 , wherein a magnitude of the voltage that is individually set differently than the corresponding one of the default voltages is different than a magnitude of the corresponding one of the default voltages.
18. The method of claim 16 , wherein the value recognized based on the message interface protocol includes at least one of an actual voltage value, an offset from the corresponding one of the default voltages, or a base voltage value and an offset from the base voltage value.
19. The method of claim 16 , wherein the value recognized based on the message interface protocol comprises a user selected value.
20. The apparatus of claim 1 , wherein all cores of the plurality of cores are architecturally identical, and wherein a first core of the plurality of cores has a first physical characteristic and a second core of the plurality of cores has a second physical characteristic that is different than the first physical characteristic.