SiC crystalline on Si substrates to allow integration of GaN and Si electronics

1. A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate, comprising:

the GaN-based device on a SiC crystalline region, wherein the SiC crystalline region is over a portion of the silicon substrate, a bottom-most surface of the GaN-based device is above a top-most surface of the silicon substrate, and the SiC crystalline region is spaced from each isolation structure of a plurality of isolation structures in the silicon substrate; and

the Si-based device in direct contact with a silicon region of the silicon substrate, wherein the silicon region directly contacts a portion of a sidewall of the SiC crystalline region adjacent a top surface of the silicon substrate, and the silicon region is adjacent to the SiC crystalline region on the silicon substrate.

2. The silicon substrate of claim 1 , wherein a surface of the SiC crystalline region is at about the same level as a surface of the silicon region.

3. The silicon substrate of claim 1 , wherein the GaN-based device is selected from the group consisting of light-emitting device, power switching device, regulator, battery protector, panel display driver, and telecommunication device.

4. The silicon substrate of claim 1 , wherein the GaN-based device is a metal-oxide-semiconductor high-electron-mobility-transistor (MOS-HEMT) or an HEMT.

5. The silicon substrate of claim 1 , wherein the Si-based device is a MOS field effect transistor (FET).

6. The silicon substrate of claim 1 , wherein the silicon substrate directly contacts a bottom surface of the SiC crystalline region.

7. The silicon substrate of claim 1 , further comprising a metal interconnect layer connecting the GaN-based device and the Si-based device.

8. A semiconductor device comprising:

a silicon substrate having a first region in the silicon substrate and a second region in the silicon substrate;

a plurality of isolation structures in the silicon substrate;

a silicon carbide (SiC) crystalline layer over the first region, wherein the SiC crystalline layer is formed by ion implantation in the silicon substrate, a sidewall of the silicon substrate directly contacts a portion of a sidewall of the SiC crystalline layer adjacent a top surface of the silicon substrate, the SiC crystalline region is spaced from each isolation structure of the plurality of isolation structures, and a top surface of the SiC crystalline layer is substantially co-planar with a top-most surface of the silicon substrate;

a gallium nitride (GaN) device formed on a top-most surface of the SiC crystalline layer; and

a metal-oxide-semiconductor (MOS) device formed on the second region.

9. The semiconductor device of claim 8 , wherein the MOS device comprises a dielectric layer over the second region, and a thickness of the dielectric layer ranges from about 100 Å to about 5000 Å.

10. The semiconductor device of claim 8 , wherein the GaN device comprises:

a GaN layer over the SiC crystalline layer;

an aluminum gallium nitride (AlGaN) layer over the GaN layer; and

a buffer layer between the GaN layer and the SiC crystalline layer.

11. The semiconductor device of claim 8 , further comprising an interconnect structure over the GaN device and the MOS device, wherein the interconnect structure electrically connects the GaN device and the MOS device.

12. The semiconductor device of claim 8 , further comprising an isolation structure between the GaN device and the MOS device.

13. The semiconductor device of claim 8 , further comprising:

a first via connected to a terminal of the GaN device; and

a second via connected to a terminal of the MOS device, wherein the first via is in a metal layer farther from the silicon substrate than the second via.

14. A semiconductor device comprising:

a silicon carbide (SiC) crystalline layer in a substrate, wherein the substrate directly contacts a portion of a sidewall of the SiC crystalline region adjacent a top surface of the substrate and a bottom surface of the SiC crystalline layer;

a plurality of isolation structures in the substrate, wherein each isolation structure of the plurality of isolation structures is spaced from the SiC crystalline region;

a first transistor on a top-most surface of the SiC crystalline layer, the first transistor having a first terminal, wherein a first direction from the SiC crystalline layer to the first transistor is normal to a top surface of the substrate, and an interface between the first transistor and the SiC crystalline layer is above a top-most surface of the substrate;

a second transistor on a silicon region of the substrate, wherein the silicon region of the substrate is spaced from the SiC crystalline layer in a second direction perpendicular to the first direction, and the second transistor has a first terminal; and

an interconnect structure configured to electrically connect the first terminal of the first transistor to the first terminal of the second transistor.

15. The semiconductor device of claim 14 , wherein the first transistor is a high electron mobility transistor (HEMT).

16. The semiconductor device of claim 14 , wherein a distance from the first terminal of the first transistor to the substrate is greater than a distance from the first terminal of the second transistor to the substrate.

17. The semiconductor device of claim 14 , wherein the first transistor comprises a group III-V compound material.

18. The semiconductor device of claim 14 , wherein an isolation structure of the plurality of isolation structures is between the first transistor and the second transistor.

19. The semiconductor device of claim 14 , further comprising a dielectric layer for isolating the interconnect structure.

20. The semiconductor device of claim 14 , wherein the second transistor is a metal-oxide-semiconductor (MOS) transistor.