Information processing device, and control method and storage medium

1. An information processing device comprising:

a processor; and

a receiving circuit coupled to the processor and configured to:

receive a packet,

determine whether a mask for suppressing generating of an interrupt is set, when the received packet is an error message for notifying occurrence of an error in communication between the processor and any of one or more other devices,

generate the interrupt when determining that the mask is not set,

transmit the generated interrupt to the processor,

set the mask,

inhibit transmitting of the interrupt to the processor, when determining that the mask for the interrupt is set, and

cancel setting of the mask when an instruction for cancelling the mask is received from the processor; and

one or more counter circuits respectively configured to:

count a number of the error message received while the mask for the interrupt is set using a counter, and

transmit a value of the number of the error message to the processor in accordance with an instruction from the processor,

wherein the receiving circuit is configured to

at a same time as one of the one or more counter circuits reads the value of the number of the error message and transmits the value to the processor, simultaneously reset the counter and cancel the setting of the mask.

2. The information processing device according to claim 1 , wherein the receiving circuit is configured to

reset the value of the number of the error message stored in any of the one or more counter circuits in accordance with the instruction from the processor.

3. The information processing device according to claim 1 ,

wherein each of the one or more counter circuits corresponds to one of the one or more other devices.

4. The information processing device according to claim 1 , further comprising:

a buffer to store the number of a plurality of error messages obtained by the one or more counter circuits,

wherein the receiving circuit is configured to read at least any of the number of a plurality of error messages from the buffer in accordance with the instruction from the processor.

5. The information processing device according to claim 1 , wherein the receiving circuit is configured to

determine whether the received packet is the error message and the mask for the interrupt is set, using an OR circuit and an AND circuit.

6. The information processing device according to claim 5 , wherein the receiving circuit is configured to:

input, to the OR circuit, a result of determining whether an error is detected from the received packet and a result of determining whether the received packet is the error message,

input, to the AND circuit, output from the OR circuit and a result of determining whether the mask for the interrupt is set, and

determine whether the received packet is the error message and the mask for the interrupt is set, based on output from the AND circuit.

7. The information processing device according to claim 1 ,

wherein the processor is configured to output information on an error included in the error message to a display device when receiving the interrupt.

8. The information processing device according to claim 1 ,

wherein the processor is configured to log information on an error included in the error message when receiving the interrupt.

9. The information processing device according to claim 1 ,

wherein the receiving circuit is coupled between the processor and the one or more other devices.

10. The information processing device according to claim 1 , wherein the receiving circuit is configured to:

determine whether the error message is received after the mask is set,

increase the number of the error message when it is determined that the error message is received.

11. The information processing device according to claim 1 , wherein the one or more counter circuits is configured to

count the number of the error message for each of one or more error levels.

12. A control method executed by an information processing device including a processor, a receiving circuit coupled to the processor and one or more counter circuits, the control method comprising:

receiving, by the receiving circuit, a packet;

determining whether a mask for suppressing generating of an interrupt is set, when the received packet is an error message for notifying occurrence of an error in communication between the processor and any of one or more other devices;

generating the interrupt when determining that the mask is not set;

transmitting the generated interrupt to the processor;

setting the mask;

inhibiting transmitting of the interrupt to the processor, when determining that the mask for the interrupt is set;

canceling setting of the mask when an instruction for cancelling the mask is received from the processor;

respectively counting, by the one or more counter circuits, a number of the error message received while the mask for the interrupt is set using a counter; and

transmitting a value of the number of the error message to the processor in accordance with an instruction from the processor,

wherein the transmitting includes

simultaneously resetting the counter and cancelling the setting of the mask at a same time of the transmitting the value of the number of the error message.

13. A non-transitory computer-readable storage medium storing a program that causes an information processing device to execute a process, the information processing device including a processor, a receiving circuit coupled to the processor and one or more counter circuits, the process comprising:

receiving, by the receiving circuit, a packet;

determining whether a mask for suppressing generating of an interrupt is set, when the received packet is an error message for notifying occurrence of an error in communication between the processor and any of one or more other devices;

generating the interrupt when determining that the mask is not set;

transmitting the generated interrupt to the processor;

setting the mask;

inhibiting transmitting of the interrupt to the processor, when determining that the mask for the interrupt is set;

canceling setting of the mask when an instruction for cancelling the mask is received from the processor;

respectively counting, by the one or more counter circuits, a number of the error message received while the mask for the interrupt is set using a counter; and

transmitting a value of the number of the error message to the processor in accordance with an instruction from the processor,

wherein the transmitting includes

simultaneously resetting the counter and cancelling the setting of the mask at a same time of the transmitting the value of the number of the error message.