Bank address remapping to load balance memory traffic among banks of memory
A system includes a processing component and a memory controller. The memory controller is to conduct memory accesses to a banked memory responsive to memory access requests from the processing component, whereby the memory controller is to distribute memory accesses among the plurality of banks by modifying, for each memory access request, a bank of the bank memory referenced by the memory access request. A memory device includes a plurality of banks, an interface to receive memory access requests, bank remapping logic, and access control logic. The bank remapping logic is to, for each received memory access request, remap a bank segment of a memory address associated with the received memory access request with a modified bank segment. The access control logic is to, for each received memory access request, access a bank of the plurality of banks based on the modified bank segment for the memory access request.
1. A system comprising:
a processing component; and
a memory controller coupled to the processing component and coupleable to a memory having a plurality of banks, the memory controller to conduct memory accesses to the memory responsive to memory access requests from the processing component, and wherein the memory controller is to distribute memory accesses among the plurality of banks by modifying, for each memory access request, a bank of the memory referenced by the memory access request by determining a modified bank segment for replacing an original bank segment of a memory address associated with the memory access request using a one-to-one function that calculates the modified bank segment using each of a plurality of bits of a row segment of the memory address, at least one bit of the original bank segment, and a rank segment of the memory address.
2. The system of claim 1 , further comprising:
the memory coupled to the memory controller.
3. The system of claim 2 , wherein the memory comprises synchronous dynamic random access memory (SDRAM).
4. The system of claim 1 , wherein the one-to-one function calculates the modified bank segment based on an XOR reduction of the plurality of bits of the row segment, the at least one bit of the original bank segment, and the rank segment.
5. A memory device comprising:
a plurality of banks;
an interface to receive memory access requests;
bank remapping logic coupled to the interface, the bank remapping logic to, for each received memory access request, remap a bank segment of a memory address associated with the received memory access request by determining a modified bank segment to replace an original bank segment of a memory address associated with the memory access request using a one-to-one function that calculates the modified bank segment using each of a plurality of bits of a row segment of the memory address, at least one bit of the original bank segment, and a rank segment of the memory address; and
access control logic coupled to the plurality of banks and the bank remapping logic, the access control logic to, for each received memory access request, access a bank of the plurality of banks based on the modified bank segment for the memory access request.
6. The memory device of claim 5 , wherein the memory device comprises synchronous dynamic random access memory (SDRAM).
7. The memory device of claim 5 , wherein the one-to-one function calculates the modified bank segment based on an XOR reduction of the plurality of bits of the row segment, the at least one bit of the original bank segment, and the rank segment.
8. In a processing system comprising a memory having a plurality of banks, a method comprising:
receiving a memory access request having a first memory address with a first bank segment and a first row segment;
generating a second bank segment based on the first memory address using a one-to-one remapping function that calculates the second bank segment using a plurality of bits of the first row segment of the first memory address, at least one bit of the first bank segment, and a rank segment of the memory address; and
conducting, for the memory access request, a memory access to a bank of the plurality of banks based on the second bank segment.
9. The method of claim 8 , wherein:
receiving the memory access request comprises receiving the memory access request at a memory controller of the processing system; and
generating the second bank segment based on the memory access comprises generating the second bank segment at the memory controller coupled to the memory.
10. The method of claim 9 , further comprising:
generating, at the memory controller, a second memory address by replacing the first bank segment with the second bank segment in the first memory address; and
wherein conducting the memory access comprises conducting the memory access request using the second memory address.
11. The method of claim 8 , wherein:
receiving the memory access request comprises receiving the memory access request at the memory; and
generating the second bank segment based on the memory access comprises generating the second bank segment at the memory.
12. The method of claim 11 , wherein the one-to-one remapping function calculates the second bank segment further based on a rank segment of the first memory address.
13. The method of claim 8 , wherein generating the second bank segment comprises generating the second bank segment without software involvement.
14. The method of claim 8 , wherein the one-to-one remapping function calculates the second bank segment based on an XOR reduction of the plurality of bits of the first row segment, the at least one bit of the original bank segment, and the rank segment.