Memory system performing read of nonvolatile semiconductor memory device
According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.
1. A memory system comprising:
a nonvolatile semiconductor memory device including a memory cell; and
a control unit configured to set a voltage supplied to the memory cell in a read,
wherein
the control unit is configured to set a first voltage supplied to the memory cell in a first read, and
the control unit is configured to set a second voltage supplied to the memory cell in a second read after a lapse of a first standing time from the first read, the second voltage different from the first voltage.
2. The memory system of claim 1 , wherein the second voltage is higher or lower than the first voltage.
3. The memory system of claim 1 , wherein a time of the first read is different from a time of the second read.
4. The memory system of claim 3 , wherein the time of the first read is different from the time of the second read by one of changing a precharge voltage of a sense node of the memory cell and changing the number of times of sense.
5. The memory system of claim 3 , wherein a third voltage supplied to an unselected word line adjacent to a selected word line in the second read is higher than a fourth voltage supplied to the unselected word line in the first read.
6. The memory system of claim 1 , wherein the control unit is configured to set the second voltage based on a standing time and an ambient temperature in the second read.
7. The memory system of claim 1 , wherein in a case that a standing time is longer than a second time, the control unit is configured to set the second voltage lower than the first voltage.
8. The memory system of claim 1 , wherein in a case that a standing time is equal or shorter than a second time, the control unit is configured to set the second voltage higher than the first voltage.
9. The memory system of claim 1 , wherein in a case that an error is detected after the first read and the second read, the control unit is configured to perform a refresh operation.