Fully differential output swing for analog array based charge mode readout used in a CMOS image sensor
Disclosed herein are novel charge mode readout circuits and associated methods of signal processing. The devices and methods of the invention allow for the improved processing of stored signals by a charge mode readout amplifier, wherein the readout level may be shifted to a desired range and wherein a fully differential output swing may be imparted. The invention advantageously employs a single pair of capacitors to serve the dual roles of modulating amplifier gain and level shifting the output.
1. A circuit comprising
a fully differential amplifier comprising a first and a second input line and a first and a second output line, the first and second output lines being branched, each such output line having a first branch and a second branch;
a pair of capacitors comprising a first and a second capacitor, each such capacitor comprising a first and a second plate;
a first and a second voltage source, each comprising an output line;
a third and fourth voltage source, each comprising an output line
an analog to digital converter comprising two inputs;
wherein
the first branch of the first output line is connected to the first plate of the first capacitor;
the second plate of the first capacitor is connected to the first input line of the amplifier;
the output line of the first voltage source is connected to the first plate of the first capacitor across a switch;
the output line of the third voltage source is connected to the second plate of the first capacitor across a switch;
the second branch of the first output line is connected to the first input of the analog to digital converter;
the first branch of the second output line is connected to the first plate of the second capacitor across a switch;
the second plate of the second capacitor is connected to the second input line of the amplifier;
the output line of the second voltage source is connected to the first plate of the second capacitor;
the second branch of the second output line is connected to the second input of the analog to digital converter; and
the second plate of the second capacitor is connected to the fourth voltage source across a switch.
2. The circuit of claim 1 , wherein
the first and second voltage sources are the two differential voltage outputs of a digital to analog converter.
3. The circuit of claim 1 , wherein the first plate of the first capacitor is connected to a first sample and hold capacitor and the first plate of the second capacitor is connected to a second sample and hold capacitor.
4. The circuit of claim 3 , wherein
the first and second sample and hold capacitors are connected to pixel output lines and store the photointegration and reset signals output from a pixel.