Semiconductor structure having low-k spacer and method of manufacturing the same
View Patent ↗The present disclosure provides a semiconductor structure, including a semiconductor fin, a metal gate over the semiconductor fin, and a sidewall spacer composed of low-k dielectric surrounding opposing sidewalls of the metal gate. A portion of the sidewall spacer comprises a tapered profile with a greater separation of the opposing sidewalls toward a top portion and a narrower separation of the opposing sidewalls toward a bottom portion of the sidewall spacer. The present disclosure also provides a method of manufacturing a semiconductor device. The method includes forming a polysilicon stripe over a semiconductor fin, forming a nitride sidewall spacer surrounding a long side of the polysilicon stripe, forming a raised source/drain region in the semiconductor fin, and forming a carbonitride etch stop layer surrounding the nitride sidewall spacer.
1. A method for manufacturing a semiconductor structure, comprising:
patterning polysilicon stripes over a semiconductor fin;
forming a sidewall spacer on the polysilicon stripes;
forming an etch stop layer surrounding the sidewall spacer;
forming a metal gate trench by removing the polysilicon stripes;
removing the sidewall spacer;
forming a low-k dielectric conformally in the metal gate trench after removing the sidewall spacer, the low-k dielectric having a dielectric constant below 3; and
removing a portion of the low-k dielectric at a bottom of the metal gate trench.
2. The method of claim 1 , further comprising:
forming a gate oxide before the formation of the polysilicon stripes;
removing the gate oxide after the removing the portion of the low-k dielectric at the bottom of the metal gate trench.
3. The method of claim 1 , further comprising:
performing a source/drain etch between the polysilicon stripes before the forming of the etch stop layer.
4. The method of claim 1 , further comprising:
forming a lightly doped region in the semiconductor fin by patterning a photoresist over the semiconductor fin; and
removing the photoresist by ashing and fluoride-based wet cleaning.
5. The method of claim 1 , wherein the removing the polysilicon stripes comprising:
performing a dry etch and followed by a wet etch.
6. The method of claim 1 , further comprising:
filling gaps between the polysilicon stripes with dielectric; and
performing a chemical mechanical polishing to expose a top surface of the polysilicon stripes.
7. The method of claim 1 , comprising using phosphoric acid to remove the sidewall spacer.
8. A method for manufacturing a semiconductor structure, comprising:
forming a polysilicon stripe over a semiconductor fin;
forming a nitride sidewall spacer surrounding a long side of the polysilicon stripe;
forming a raised source/drain region in the semiconductor fin, abutting the polysilicon stripe; and
forming a carbonitride etch stop layer surrounding the nitride sidewall spacer;
removing the nitride sidewall spacer until exposing a sidewall of the carbonitride etch stop layer; and
forming a low-k dielectric in contact with the sidewall of the exposed carbonitride etch stop layer.
9. The method of claim 8 , further comprising:
planarize the polysilicon stripe by gap filling; and
removing the polysilicon stripe.
10. The method of claim 8 , further comprising:
removing a bottom portion of the low-k dielectric by a dry etch, thereby forming a tapered opening at a top portion of the low-k dielectric and a footing in proximity to the bottom portion of the low-k dielectric.
11. The method of claim 10 , further comprising:
forming a gate oxide before the formation of the polysilicon stripe; and
removing the gate oxide after the removing the bottom portion of the low-k dielectric.
12. The method of claim 8 , further comprising:
using the polysilicon stripe and the nitride sidewall spacer as a hardmask to form a lightly doped region in the semiconductor fin.
13. A method for manufacturing a semiconductor structure, comprising:
forming a polysilicon stripe over and orthogonal to a semiconductor fin;
forming a sidewall spacer of a first material surrounding a long side of the polysilicon stripe;
forming an etch stop layer of a second material surrounding the sidewall spacer, wherein the first material and the second material have different etching rates with respect to an etchant;
removing the sidewall spacer until exposure of a sidewall of the etch stop layer; and
forming a comformal low-k dielectric in contact with the sidewall of the exposed etch stop layer, the low-k dielectric having a dielectric constant below 3.
14. The method of claim 13 , further comprising:
removing a bottom portion of the low-k dielectric by a dry etch, thereby forming a tapered opening at a top portion of the low-k dielectric and a footing in proximity to the bottom portion of the low-k dielectric.
15. The method of claim 14 , further comprising:
forming a gate oxide before the formation of the polysilicon stripe; and
removing the gate oxide after the removing the bottom portion of the low-k dielectric.
16. The method of claim 13 , wherein the first material comprises nitride and the second material comprises carbonitride.
17. The method of claim 13 , wherein the etchant comprises phosphoric acid.
18. The method of claim 13 , further comprising removing the polysilicon stripe before removing the sidewall spacer.