Interconnect structure and methods of forming the same
View Patent ↗An interconnect structure, along with methods of forming such, are described. In some embodiments, the method includes forming a first dielectric layer over one or more devices, forming a first conductive feature in the first dielectric layer, and forming two dielectric features over the first dielectric layer and the first conductive feature. At least one of the two dielectric features has a first width, and each dielectric feature includes a first low-k dielectric layer, an oxide layer, and a first etch stop layer. The method further includes forming a second conductive feature between the two dielectric features, and the second conductive feature has a second width substantially the same as the first width.
1. A method, comprising:
depositing a first dielectric layer over a substrate;
depositing an etch stop layer on the first dielectric layer;
depositing an oxide layer on the etch stop layer;
depositing a sacrificial layer over the first dielectric layer, wherein the sacrificial layer is deposited on the oxide layer;
patterning the sacrificial layer to form a plurality of portions of the sacrificial layer;
depositing a conformal dielectric layer around the plurality of portions of the sacrificial layer;
removing horizontal portions of the conformal dielectric layer;
removing the plurality of portions of the sacrificial layer, comprising:
depositing a multilayer structure on vertical portions of the conformal dielectric layer and the plurality of portions of the sacrificial layer; and
patterning the multilayer structure to expose the plurality of portions of the sacrificial layer; and
removing the multilayer structure to expose the vertical portions of the conformal dielectric layer.
2. The method of claim 1 , wherein the removing of the plurality of portions of the sacrificial layer and the removing of the multilayer structure expose portions of the oxide layer.
3. The method of claim 2 , further comprising removing the exposed portions of the oxide layer and portions of the etch stop layer to expose portions of the first dielectric layer.
4. The method of claim 3 , further comprising depositing a conductive material in contact with the vertical portions of the conformal dielectric layer, the oxide layer, the etch stop layer, and the exposed portions of the first dielectric layer.
5. A method, comprising:
depositing an etch stop layer over a substrate;
depositing an oxide layer on the etch stop layer;
depositing a sacrificial layer over the substrate, wherein the sacrificial layer is deposited on the oxide layer;
patterning the sacrificial layer to form a plurality of openings in the sacrificial layer;
forming a first low-k dielectric layer adjacent the patterned sacrificial layer, wherein the first low-k dielectric layer partially fills the plurality of openings, and the first low-k dielectric layer is formed by depositing a dielectric layer and removing horizontal portions of the dielectric layer;
forming a structure over the patterned sacrificial layer and the first low-k dielectric layer, wherein the structure fills the plurality of openings;
removing the patterned sacrificial layer; and
removing the structure.
6. The method of claim 5 , wherein the dielectric layer is deposited by atomic layer deposition.
7. The method of claim 5 , wherein the removing of the patterned sacrificial layer and the removing of the structure expose portions of the oxide layer.
8. The method of claim 7 , further comprising removing the exposed portions of the oxide layer and portions of the etch stop layer, wherein the first low-k dielectric layer and the remaining portions of the oxide layer and the etch stop layer form a plurality of dielectric features.
9. The method of claim 8 , further comprising depositing a conductive material around the plurality of dielectric features.
10. The method of claim 9 , further comprising removing a portion of the conductive material to expose the first low-k dielectric layer.
11. The method of claim 10 , further comprising forming a second low-k dielectric layer over the conductive material and the first low-k dielectric layer.
12. A method, comprising:
forming a sacrificial layer over a substrate;
forming a multilayer structure on the sacrificial layer, wherein the multilayer structure comprises one or more layers;
removing portions of the one or more layers by a first plasma etch process in an etch chamber, wherein the first plasma etch process comprises using a first frequency;
removing portions of the sacrificial layer to form a patterned sacrificial layer having a plurality of openings by a second plasma etch process in the etch chamber, wherein the second plasma etch process comprises using a second frequency substantially less than the first frequency;
depositing a dielectric layer on the patterned sacrificial layer; and
depositing a conductive material adjacent the dielectric layer.
13. The method of claim 12 , wherein the dielectric layer is deposited by atomic layer deposition.
14. The method of claim 12 , further comprising removing portions of the dielectric layer.
15. The method of claim 14 , further comprising removing the patterned sacrificial layer.
16. The method of claim 12 , wherein the first frequency ranges from about 12.88 MHz to about 14.24 MHz.
17. The method of claim 16 , wherein the second frequency ranges from about 1.9 MHz to about 2.1 MHz.
18. The method of claim 12 , wherein the etch chamber is a dual-frequency etch chamber configured to change the frequency from the first frequency to the second frequency.
19. The method of claim 12 , wherein the second plasma etch process comprises chemical and physical etches.
20. The method of claim 19 , wherein the second plasma etch process use a chlorine-containing or bromine-containing etchant.