Plasma etching apparatus, plasma etching method, and semiconductor device fabrication method including the plasma etching method
Disclosed are plasma etching apparatuses, plasma etching methods, and semiconductor device fabrication methods. The plasma etching apparatus comprises a chamber, an electrostatic chuck in a lower portion of the chamber, a radio-frequency power supply that has a connection with the electrostatic chuck and provides the electrostatic chuck with a radio-frequency power to generate a plasma in the chamber, and a controller that has a connection with the radio-frequency power supply and controls the radio-frequency power.
1. A plasma etching method, comprising:
providing a plasma etching chamber having a gas supply, an electrostatic chuck having thereon a sample to be etched, a radio frequency source inducing a plasma on the sample, and a controller;
providing a gas from the gas supply to the etching chamber;
providing the electrostatic chuck with a first radio-frequency power having a first frequency;
providing the electrostatic chuck with a second radio-frequency power having a second frequency, the second radio-frequency power being greater than the first radio-frequency power, and the second frequency being less than the first frequency; and
providing the electrostatic chuck with a third radio-frequency power having a third frequency, the third radio-frequency power being less than the second radio-frequency power, and the third frequency being less than the second frequency,
wherein the second radio-frequency power is from 3 times to 5 times the first radio-frequency power.
2. The plasma etching method of claim 1 , wherein the second radio-frequency power is about 4 times the first radio-frequency power and the third radio-frequency power.
3. The plasma etching method of claim 1 , wherein a phase of the second radio-frequency power precedes a phase of the third radio-frequency power by about 7 C radians.
4. The plasma etching method of claim 1 , wherein
the first radio-frequency power has a first pulse including a first inclined duration,
the second radio-frequency power has a second pulse including a second inclined duration longer than the first inclined duration, and
the third radio-frequency power has a third pulse including a third inclined duration longer than the second inclined duration.
5. The plasma etching method of claim 4 wherein
the first inclined duration lasts for about 10 microseconds to about 15 microseconds,
the second inclined duration lasts for about 20 microseconds to about 25 microseconds, and
the third inclined duration lasts for about 30 microseconds to about 35 microseconds.
6. A semiconductor device fabrication method, comprising:
allowing an electrostatic chuck to load a substrate having an etch target; and
etching the etch target using a plasma,
wherein etching the etch target includes:
providing the electrostatic chuck with a first radio-frequency power having a first frequency;
providing a second radio-frequency power having a second frequency, the second radio-frequency power being greater than the first radio-frequency power, and the second frequency being less than the first frequency; and
providing a third radio-frequency power having a third frequency, the third radio-frequency power being less than the second radio-frequency power, and the third frequency being less than the second frequency,
wherein the second radio-frequency power is from 3 times to 5 times the first radio-frequency power.
7. The semiconductor device fabrication method of claim 6 , wherein the etch target includes a mold dielectric layer,
wherein etching the etch target includes removing a portion of the mold dielectric layer to form a channel hole.
8. The semiconductor device fabrication method of claim 7 , further comprising:
forming a vertical insulator and a first semiconductor pattern on an inner wall of the channel hole;
forming a channel structure on the vertical insulator, the first semiconductor pattern, and the substrate; and
forming a trench by partially etching the mold dielectric layer between a plurality of channel holes.
9. The semiconductor device fabrication method of claim 8 , further comprising:
forming a recess region by removing a sacrificial layer of the mold dielectric layer, the sacrificial layer being exposed to the trench;
forming a horizontal insulator and a gate electrode in the recess region;
forming a common source region on the substrate in the trench;
forming an electrode isolation pattern in the trench on the common source region; and
forming a contact plug and a bit line on the first semiconductor pattern and the channel structure.
10. The semiconductor device fabrication method of claim 7 , wherein an aspect ratio of the channel hole is greater than about 70:1.