Etch profile control of gate contact opening

1. A method comprising:

forming a gate structure over a semiconductor substrate;

forming an etch stop layer over the gate structure and an interlayer dielectric (ILD) layer over the etch stop layer;

performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, resulting in a sidewall of the etch stop layer being exposed in the gate contact opening;

oxidizing the exposed sidewall of the etch stop layer;

after oxidizing the exposed sidewall of the etch stop layer, performing a second etching process to deepen the gate contact opening; and

forming a gate contact in the deepened gate contact opening.

2. The method of claim 1 , wherein the sidewall of the etch stop layer is oxidized using an oxygen plasma.

3. The method of claim 2 , wherein the oxygen plasma is generated from an O2 gas.

4. The method of claim 2 , wherein the oxygen plasma is generated from a gaseous mixture of an O 2 gas and one or more of an Ar gas, a He gas, a Ne gas, a Kr gas, a N 2 gas, a CO gas, a CO 2 gas, a C x H y F z gas, a NF 3 gas, a Carbonyl sulfide (COS) gas, and a SO 2 gas, wherein x, y and z are greater than zero and not greater than nine.

5. The method of claim 1 , wherein the second etching process uses a different etchant than that used in the first etching process.

6. The method of claim 1 , wherein the first etching process is a plasma etching process using a plasma generated from a hydrogen-free gaseous mixture.

7. The method of claim 1 , wherein the second etching process is a plasma etching process using a plasma generated from a hydrogen-containing gaseous mixture.

8. The method of claim 7 , wherein the hydrogen-containing gaseous mixture is a mixture of a fluorine-containing gas and a hydrogen gas.

9. The method of claim 8 , wherein the fluorine-containing gas is a CHF 3 gas, a CF 4 gas, or a combination thereof.

10. The method of claim 1 , wherein the second etching process etches the oxidized sidewall of the etch stop layer at a slower etch rate than etching an un-oxidized region of the etch stop layer.

11. A method comprising:

forming a gate structure between gate spacers;

depositing in sequence an etch stop layer and an interlayer dielectric (ILD) layer over the gate structure;

performing a first etching process to form a gate contact opening in the ILD layer at least until the etch stop layer is exposed;

after performing the first etching process, performing an oxygen plasma treatment to form a treated region in the etch stop layer and around a bottom portion of the gate contact opening, while leaving a remaining region of the etch stop layer un-treated;

after performing the oxygen plasma treatment, performing a second etching process to extend the gate contact opening toward the gate structure, wherein the treated region of the etch stop layer has a higher etch resistance than the un-treated region of the etch stop layer in the second etching process; and

after performing the second etching process, forming a gate contact in the gate contact opening.

12. The method of claim 11 , further comprising:

etching back the gate structure to fall below top ends of the gate spacers;

forming a gate dielectric cap over the etched back gate structure; and

after forming the gate dielectric cap, forming source/drain contacts abutting opposite sides of the gate dielectric cap,

wherein the etch stop layer is deposited over the source/drain contacts and the gate dielectric cap, and the first etching process is performed such that the gate dielectric cap is exposed.

13. The method of claim 12 , wherein the oxygen plasma treatment forms a treated region in the gate dielectric cap and an un-treated region below the treated region in the gate dielectric cap.

14. The method of claim 13 , wherein the second etching process breaks through the gate dielectric cap, and the second etching process etches the treated region in the gate dielectric cap at a slower etch rate than etching the un-treated region in the gate dielectric cap.

15. The method of claim 12 , further comprising:

prior to forming the gate dielectric cap, forming a gate metal cap over the etched back gate structure, wherein the second etching process is performed such that the gate metal cap is exposed.

16. The method of claim 12 , further comprising:

etching back the gate spacers, wherein the gate dielectric cap is also formed over the etched back gate spacers.

17. A device comprising:

a gate structure over a substrate;

an etch stop layer over the gate structure;

an interlayer dielectric (ILD) layer over the etch stop layer; and

a gate contact extending through the ILD layer and the etch stop layer to electrically connect with the gate structure, wherein the etch stop layer has a first oxidized region laterally surrounding the gate contact and a first un-oxidized region laterally surrounding the first oxidized region.

18. The device of claim 17 , further comprising:

source/drain contacts on opposite sides of the gate structure, respectively; and

a gate dielectric cap over the gate structure and having opposite sidewalls respectively contacting the source/drain contacts, wherein the gate contact also extends through the gate dielectric cap, and the gate dielectric cap has a second oxidized region laterally surrounding the gate contact and a second un-oxidized region under the second oxidized region.

19. The device of claim 18 , wherein the second oxidized region of the gate dielectric cap extends continuously from the first oxidized region of the etch stop layer, and terminates prior to reaching a bottommost position of the gate contact.

20. The device of claim 18 , wherein the second un-oxidized region of the gate dielectric cap is in contact with the gate contact.