Via structure and methods thereof

1. A semiconductor device, comprising:

a substrate;

a bottom etch stop layer over the substrate;

a middle etch stop layer over the bottom etch stop layer;

a top etch stop layer over the middle etch stop layer, wherein the top, middle, and bottom etch stop layers include different material compositions from each other, and wherein the top and bottom etch stop layers include a same metallic element;

a dielectric layer over the top etch stop layer; and

a via extending through the dielectric layer and the top, middle, and bottom etch stop layers, wherein the via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.

2. The semiconductor device of claim 1 , wherein the first and second sidewalls intersect below a top surface of the top etch stop layer.

3. The semiconductor device of claim 1 , wherein the first and second sidewalls intersect below a top surface of the middle etch stop layer.

4. The semiconductor device of claim 1 , wherein the first and second sidewalls intersect at a top surface of the bottom etch stop layer.

5. The semiconductor device of claim 1 , wherein the via has a third sidewall in contact with the bottom etch stop layer and slanted inwardly from top to bottom towards the center of the via, wherein the third sidewall is below the second sidewall.

6. The semiconductor device of claim 1 , wherein the via includes a barrier layer extending continuously through the dielectric layer and the top, middle, and bottom etch stop layers.

7. The semiconductor device of claim 1 , wherein the metallic element is aluminum.

8. The semiconductor device of claim 1 , wherein the bottom etch stop layer is an oxide layer, the middle etch stop layer is a carbide layer, and the top etch stop layer is a nitride layer.

9. The semiconductor device of claim 1 , wherein the via has a bottom surface and a top surface, and wherein the bottom surface has a larger area than the top surface.

10. A semiconductor device, comprising:

a substrate;

a first dielectric layer over the substrate;

a second dielectric layer over the first dielectric layer, the first and second dielectric layers having different material compositions; and

a via extending through the second and first dielectric layers, the via having an upper portion disposed above a boundary of the first and second dielectric layers and a lower portion disposed below the boundary, the lower portion having a first width measured at the boundary, a second width measured at a bottom of the via, and a third width measured between the boundary and the bottom of the via, wherein the third width is larger than the second width and the second width is larger than the first width, wherein the first width is larger than a smallest width of the via from top to bottom, and wherein the first width and the smallest width are located at different heights measured from a top surface of the substrate.

11. The semiconductor device of claim 10 , wherein the smallest width of the via locates within the first dielectric layer.

12. The semiconductor device of claim 10 , wherein the third width is about 5% to about 10% larger than the second width.

13. The semiconductor device of claim 10 , wherein the third width achieves a largest value in a lower half portion of the first dielectric layer.

14. The semiconductor device of claim 10 , wherein the first dielectric layer includes a metal oxide.

15. The semiconductor device of claim 14 , wherein the first dielectric layer includes at least a layer of the metal oxide and a layer of a metal nitride.

16. The semiconductor device of claim 10 , wherein the substrate includes a conductive feature in physical contact with the via, and wherein the conductive feature is a gate terminal or a source/drain terminal of a transistor.

17. An integrated circuit structure, comprising:

a substrate;

an etch stop layer over the substrate, the etch stop layer including at least a first sub layer and a second sub layer over the first sub layer, one of the first and second sub layers containing a metal oxide, and another one of the first and second sub layers containing a metal nitride;

a low-k dielectric layer over the etch stop layer; and

a conductive feature extending through the low-k dielectric layer and the etch stop layer, wherein the conductive feature has an upper portion disposed in the low-k dielectric layer and a lower portion disposed in the etch stop layer, wherein the lower portion has a largest width located below a top surface of the etch stop layer and a smallest width located at or below a bottom surface of the second sub layer and above where the largest width is located, the smallest width being smaller than the largest width.

18. The integrated circuit structure of claim 17 , wherein a footing of the conductive feature has a rounded corner.

19. The integrated circuit structure of claim 17 , wherein the etch stop layer includes one or more of: aluminum nitride, aluminum oxide, and silicon carbide.

20. The integrated circuit structure of claim 17 , wherein the metal oxide and the metal nitride include a same metal element.