IP Library Granted Patent US 10,332,906
Granted Patent B2
US 10,332,906 · App. 15/661,243 · Granted Jun 25, 2019

Dry etching method and method for manufacturing semiconductor device

Inventors: Kaori Narumiya (Yokkaichi Mie, JP); Hisataka Hayashi (Yokkaichi Mie, JP); Keisuke Kikutani (Yokkaichi Mie, JP); Akio Ui (Tokyo, JP); Yosuke Sato (Kanagawa, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11582H01J37/32706H01L21/31116H01L21/32136H01L21/32137H01L27/1157H01L27/11575H01J2237/334
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,332,906
App. No.
15/661,243
Granted
Jun 25, 2019
Kind
B2
Abstract

A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member. A time for which the bias power is continuously applied is set to 50 microseconds or less and a duty ratio of the bias power is set to 50% or less.

Claims (30)

1. A dry etching method comprising:

a first process of, while applying bias power to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member by using an ion species generated by applying the bias power,

wherein the bias power is applied during a first period, a time for which is set to 50 microseconds or less,

wherein the bias power is applied during a second period such that a ratio of the first period to a time for the second period is set to 50% or less,

wherein the second conductive member is electrically insulated from the first conductive member,

wherein the bias power applied during the first period is a superimposed wave of first alternating-current power with a first frequency, second alternating-current power with a second frequency lower than the first frequency, and a pulse signal with a third frequency lower than the second frequency.

2. The dry etching method according to claim 1 , wherein the time for the second period is set to 50 microseconds or more.

3. The dry etching method according to claim 1 , wherein the second conductive member is not exposed at a surface of the material to be processed.

4. The dry etching method according to claim 1 , further comprising:

before the first process, a second process of, while applying bias power using an ion species, etching the second insulating film without exposing the second conductive member,

wherein the a duty ratio of the bias power of the second process is set to 100%.

5. The dry etching method according to claim 4 , wherein, in the second process, the bias power is continuously applied or is intermittently applied at a duty ratio higher than the ratio of the time for the first period to the time for the second period.

6. The dry etching method according to claim 4 , further comprising:

after the second process and before the first process, a third process of not applying bias power.

7. A method for manufacturing a semiconductor device, comprising:

a first process of, while applying bias power to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, etching the second insulating film to expose the second conductive member by using an ion species generated by applying the bias power,

wherein the bias power is applied during a first period, a time for which is set to 50 microseconds or less,

wherein the bias power is applied during a second period such that a ratio of the time for the first period to a time for the second period is set to 50% or less,

wherein the second conductive member is electrically insulated from the first conductive member,

wherein the bias power applied during the first period is a superimposed wave of first alternating-current power with a first frequency, second alternating-current power with a second frequency lower than the first frequency, and a pulse signal with a third frequency lower than the second frequency.

8. The method for manufacturing a semiconductor device, according to claim 7 , further comprising:

a second process of forming the second insulating film by alternately stacking a silicon oxide layer and a silicon nitride layer in layers.

9. The method for manufacturing a semiconductor device, according to claim 7 , wherein the time for the second period is set to 50 microseconds or more.

10. The method for manufacturing a semiconductor device, according to claim 7 , wherein the second conductive member is not exposed at a surface of the material to be processed.

11. The method for manufacturing a semiconductor device, according to claim 7 , further comprising:

before the first process, a second process of, while applying bias power using an ion species, etching the second insulating film without exposing the second conductive member,

wherein the a duty ratio of the bias power of the second process is set to 100%.

12. The method for manufacturing a semiconductor device, according to claim 11 , wherein, in the second process, the bias power is continuously applied or is intermittently applied at a duty ratio higher than the ratio of the time for the first period to the time for the second period.

13. The method for manufacturing a semiconductor device, according to claim 11 , further comprising:

after the second process and before the first process, a third process without applying bias power.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: NARUMIYA, KAORI; HAYASHI, HISATAKA; KIKUTANI, KEISUKE; UI, AKIO; SATO, YOSUKE
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043116/0666 →
Priority Claims (1)
JP 2016-226298 · Nov 21, 2016 · national
Continuity (1)
Related Publication 20180145086A1 · May 24, 2018
Cited By (1)
US 12,368,076