Semiconductor device and semiconductor device manufacturing method
A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.
1. A semiconductor device comprising:
a semiconductor substrate;
a front surface electrode provided on a front surface of the semiconductor substrate; and
a rear surface electrode provided on a rear surface of the semiconductor substrate;
the semiconductor substrate comprising:
an element region in which an insulated gate type switching element configured to switch between the front surface electrode and the rear surface electrode is provided; and
a circumferential region adjacent to the element region; and
the insulated gate type switching element comprising:
a first region of a first conductivity type connected to the front surface electrode;
a second region of a second conductivity type connected to the front surface electrode and being in contact with the first region;
a third region of the first conductivity type provided under the second region and separated from the first region by the second region;
a gate insulating film being in contact with the second region; and
a gate electrode facing the second region via the gate insulating film,
wherein a first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region,
insulating films are provided in the first trench and the second trench,
a front surface region of the second conductivity type is provided in a front surface side portion of a region between the first trench and the second trench,
a first bottom surface region of the second conductivity type is provided in a range exposed on a bottom surface of the first trench,
a second bottom surface region of the second conductivity type is provided in a range exposed on a bottom surface of the second trench,
a first side surface region of the second conductivity type connecting the front surface region and the first bottom surface region is provided along a side surface of the first trench,
a second side surface region of the second conductivity type connecting the front surface region and the second bottom surface region is provided along a side surface of the second trench, and
a fourth region of the first conductivity type continuous from the third region is provided in a range where the fourth region is in contact with the front surface region, the first bottom surface region, the second bottom surface region, the first side surface region, and the second side surface region,
a first low area density region is provided in at least a part of the first side surface region,
an area density of second conductivity type impurities in the first low area density region measured along a direction perpendicular to the side surface of the first trench is lower than an area density of second conductivity type impurities in the first bottom surface region measured along a thickness direction of the semiconductor substrate,
the first bottom surface region is separated from the front surface region by the first low area density region,
a second low area density region is provided in at least a part of the second side surface region,
an area density of second conductivity type impurities in the second low area density region measured along a direction perpendicular to the side surface of the second trench is lower than an area density of second conductivity type impurities in the second bottom surface region measured along the thickness direction of the semiconductor substrate,
the second bottom surface region is separated from the front surface region by the second low area density region,
the semiconductor substrate is configured of SiC, and
the area density in the first low area density region and the area density in the second low area density region are lower than 3.2×10 13 cm −2 .
2. A semiconductor device comprising:
a semiconductor substrate;
a front surface electrode provided on a front surface of the semiconductor substrate; and
a rear surface electrode provided on a rear surface of the semiconductor substrate;
the semiconductor substrate comprising:
an element region in which an insulated gate type switching element configured to switch between the front surface electrode and the rear surface electrode is provided; and
a circumferential region adjacent to the element region; and
the insulated gate type switching element comprising:
a first region of a first conductivity type connected to the front surface electrode;
a second region of a second conductivity type connected to the front surface electrode and being in contact with the first region;
a third region of the first conductivity type provided under the second region and separated from the first region by the second region;
a gate insulating film being in contact with the second region; and
a gate electrode facing the second region via the gate insulating film,
wherein a first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region,
insulating films are provided in the first trench and the second trench,
a front surface region of the second conductivity type is provided in a front surface side portion of a region between the first trench and the second trench,
a first bottom surface region of the second conductivity type is provided in a range exposed on a bottom surface of the first trench,
a second bottom surface region of the second conductivity type is provided in a range exposed on a bottom surface of the second trench,
a first side surface region of the second conductivity type connecting the front surface region and the first bottom surface region is provided along a side surface of the first trench,
a second side surface region of the second conductivity type connecting the front surface region and the second bottom surface region is provided along a side surface of the second trench, and
a fourth region of the first conductivity type continuous from the third region is provided in a range where the fourth region is in contact with the front surface region, the first bottom surface region, the second bottom surface region, the first side surface region, and the second side surface region,
a first low area density region is provided in at least a part of the first side surface region,
an area density of second conductivity type impurities in the first low area density region measured along a direction perpendicular to the side surface of the first trench is lower than an area density of second conductivity type impurities in the first bottom surface region measured along a thickness direction of the semiconductor substrate,
the first bottom surface region is separated from the front surface region by the first low area density region,
a second low area density region is provided in at least a part of the second side surface region,
an area density of second conductivity type impurities in the second low area density region measured along a direction perpendicular to the side surface of the second trench is lower than an area density of second conductivity type impurities in the second bottom surface region measured along the thickness direction of the semiconductor substrate,
the second bottom surface region is separated from the front surface region by the second low area density region,
the semiconductor substrate is configured of Si, and
the area density in the first low area density region and the area density in the second low area density region are lower than 2.0×10 12 cm −2 .
3. A semiconductor device comprising:
a semiconductor substrate;
a front surface electrode provided on a front surface of the semiconductor substrate; and
a rear surface electrode provided on a rear surface of the semiconductor substrate;
the semiconductor substrate comprising:
an element region in which an insulated gate type switching element configured to switch between the front surface electrode and the rear surface electrode is provided; and
a circumferential region adjacent to the element region; and
the insulated gate type switching element comprising:
a first region of a first conductivity type connected to the front surface electrode;
a second region of a second conductivity type connected to the front surface electrode and being in contact with the first region;
a third region of the first conductivity type provided under the second region and separated from the first region by the second region;
a gate insulating film being in contact with the second region; and
a gate electrode facing the second region via the gate insulating film,
wherein a first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region,
insulating films are provided in the first trench and the second trench,
a front surface region of the second conductivity type is provided in a front surface side portion of a region between the first trench and the second trench,
a first bottom surface region of the second conductivity type is provided in a range exposed on a bottom surface of the first trench,
a second bottom surface region of the second conductivity type is provided in a range exposed on a bottom surface of the second trench,
a first side surface region of the second conductivity type connecting the front surface region and the first bottom surface region is provided along a side surface of the first trench,
a second side surface region of the second conductivity type connecting the front surface region and the second bottom surface region is provided along a side surface of the second trench, and
a fourth region of the first conductivity type continuous from the third region is provided in a range where the fourth region is in contact with the front surface region, the first bottom surface region, the second bottom surface region, the first side surface region, and the second side surface region,
a first low area density region is provided in at least a part of the first side surface region,
an area density of second conductivity type impurities in the first low area density region measured along a direction perpendicular to the side surface of the first trench is lower than an area density of second conductivity type impurities in the first bottom surface region measured along a thickness direction of the semiconductor substrate,
the first bottom surface region is separated from the front surface region by the first low area density region,
a second low area density region is provided in at least a part of the second side surface region,
an area density of second conductivity type impurities in the second low area density region measured along a direction perpendicular to the side surface of the second trench is lower than an area density of second conductivity type impurities in the second bottom surface region measured along the thickness direction of the semiconductor substrate,
the second bottom surface region is separated from the front surface region by the second low area density region, and
the first low area density region and the second low area density region are depleted when a maximum rated voltage is applied to the insulated gate type switching device in an off state.
4. The semiconductor device of claim 1 , wherein
the semiconductor substrate is configured of SiC, and
the area density in the first bottom surface region and the area density in the second bottom surface region are equal to or higher than 1.5×10 13 cm −2 .
5. The semiconductor device of claim 2 , wherein
the semiconductor substrate is configured of Si, and
the area density in the first bottom surface region and the area density in the second bottom surface region are equal to or higher than 1.9×10 12 cm −2 .
6. The semiconductor device of claim 3 , wherein at least a part of the first bottom surface region and at least a part of the second bottom surface region are not depleted when a maximum rated voltage is applied to the insulated gate type switching device in an off state.
7. A method for manufacturing the semiconductor device of claim 1 , the method comprising:
forming the first trench and the second trench in the front surface of the semiconductor substrate in the circumferential region and forming a gate trench in the front surface of the semiconductor substrate in the element region so that a taper angle of the first trench and a taper angle of the second trench are larger than a taper angle of the gate trench;
forming a protective film on inner surfaces of the first trench, the second trench, and the gate trench; and
implanting second conductivity type impurities to the semiconductor substrate,
wherein, in the implantation, the second conductivity impurities pass through the protective film on a bottom surface of the gate trench so as to be implanted to the bottom surface of the gate trench, the second conductivity impurities are prevented from being implanted to the side surface of the gate trench by the protective film on the side surface of the gate trench, the second conductivity impurities pass through the protective film on the bottom surfaces of the first and second trenches so as to be implanted to the bottom surfaces of the first and second trenches, and the second conductivity impurities pass through the protective film on the side surfaces of the first and second trenches so as to be implanted to the side surfaces of the first and second trenches.
8. A method for manufacturing the semiconductor device of claim 1 , the method comprising:
forming the first trench and the second trench in the front surface of the semiconductor substrate in the circumferential region and forming a gate trench in the front surface of the semiconductor substrate in the element region; and
implanting second conductivity type impurities to the front surface of the semiconductor substrate at an oblique angle in a state where a circumferential region mask having openings corresponding to the first trench and the second trench is provided on the front surface of the semiconductor substrate in the circumferential region and an element region mask thicker than the circumferential region mask and having an opening corresponding to the gate trench is provided on the front surface of the semiconductor substrate in the element region,
wherein, in the implantation, the second conductivity impurities are implanted to the side surfaces of the first and second trenches and prevented from being implanted to the side surface of the gate trench by the element region mask.
9. A method for manufacturing the semiconductor device of claim 1 , comprising:
forming the first trench and the second trench in the front surface of the semiconductor substrate in the circumferential region and forming the gate trench in the front surface of the semiconductor substrate in the element region so that a taper angle of the first trench and a taper angle of the second trench are larger than a taper angle of the gate trench;
forming a protective film on inner surfaces of the first trench, the second trench, and the gate trench;
removing the protective film located on the side surfaces and the bottom surfaces of the first and second trenches and on the bottom surface of the gate trench by anisotropic etching; and
implanting second conductivity type impurities to the semiconductor substrate,
wherein, in the implantation, the second conductivity type impurities are implanted to the side surfaces and the bottom surfaces of the first and second trenches and the bottom surface of the gate trench, and are prevented from being implanted to the side surface of the gate trench by the protective film.