IP Library Granted Patent US 10,020,733
Granted Patent B2
US 10,020,733 · App. 15/492,884 · Granted Jul 10, 2018

Adaptive controller for a voltage converter

Inventor: Jianzhang Xie (Shanghai, CN)
Assignee: Texas Instruments Incorporated
H02M3/158H02M3/1588H02M1/08H02M2001/0054Y02B70/1466Y02B70/1491
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Quick Facts
Patent No.
US 10,020,733
App. No.
15/492,884
Granted
Jul 10, 2018
Kind
B2
Abstract

A DC-to-DC converter includes an input voltage node, an inductor, and a switch coupled to the inductor and the input voltage node. More specifically, the switch has an on state and off state, wherein during the on state, current flowing through the inductor increases and the off state results in a decrease of the current flowing through the inductor via a driver coupled to the switch. The driver comprises a plurality of transistors and an adaptive voltage node, wherein a voltage level at the adaptive voltage node is to vary in accordance with the current flowing through the inductor so as to decrease a variation of the amount of time to turn off the switch.

Claims (12)

1. A controller for a DC-DC converter comprising a MOSFET low side switch transistor having a parasitic gate capacitance which must be discharged to turn off the transistor, the controller comprising:

a circuit for generating a load signal representative of a load current through an inductor; and

a driver circuit coupled to a gate of the MOSFET low side switch transistor responsive to the load signal and providing a control signal to the gate to discharge the gate capacitance and the control signal varying inversely to the load current through the inductor.

2. The controller of claim 1 wherein the load current through the transistor is: iL=iD+iG, where iL equals load current, iD equals conductance current and iG equals a discharging current flowing through the parasitic gate capacitance.

3. The controller of claim 2 wherein the discharging current is

Vgs_M 1 /(Ron_M 11 +Ron_M 12 ), where Vgs_M 1 represents a voltage drop across the gate and source terminals of the low side switch, Ron_M 11 +Ron_M 12 represent a conductor resistance for transistors located between the gate of the low side switch and ground.

4. The controller of claim 3 wherein during switching of the low side transistor, Vgs_M 1 equals V th+K√{square root over ((i L))}, where V_th is a threshold voltage of the low side switch transistor, K is a proportional constant and i_L is the load current.

5. The controller of claim 1 comprising a driver coupled to first and second switches and configured to alternately turn on and off the first and second switches, the driver including two transistors connected in series, the amount of time to turn off the first switch being based on a value of a conductive resistance from each of the two transistors and a voltage drop between gate and source terminals of the first switch.

6. The controller of claim 5 in which the driver is configured to receive a pulse width modulated (PWM) signal that is used to alternately turn on and off the first and second switches.

7. The controller of claim 5 in which the voltage drop between the gate and source terminals of the first switch varies with the current that flows through the inductor.

8. The controller of claim 5 comprising when the first switch is off, the driver provides a voltage level to an adaptive voltage node, the voltage level being inversely proportional to the current that flows through the inductor so as to decrease a variation of the amount of time to turn off the first switch wherein the first switch is a power metal oxide field effect transistor (MOSFET).

9. The controller of claim 8 comprising one of the two transistors being connected to the adaptive voltage node, and the value of the conductive resistance of such transistor varying accordingly with the voltage level at the adaptive voltage node.

Continuity (3)
Division 14631178 · Feb 25, 2015
Continuation PCTCN2014089451 · Oct 24, 2014
Related Publication 20170324327A1 · Nov 9, 2017
Cited By (1)
US 12,295,217