IP Library Granted Patent US 10,025,897
Granted Patent B2
US 10,025,897 · App. 15/019,078 · Granted Jul 17, 2018

Generation of circuit design populations for analog circuit design optimization

Inventors: Sowmyan Rajagopalan (Pontypool, GB); Christopher M. Yates (Wiltshire, GB)
Assignee: Thalia Design Automation Ltd.
G06F17/5063G06F17/5036
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Quick Facts
Patent No.
US 10,025,897
App. No.
15/019,078
Granted
Jul 17, 2018
Kind
B2
Abstract

A method for analog circuit design includes the steps of (A) evaluating an initial population comprising a plurality of initial designs of an analog circuit using a computer to determine to breed a plurality of new designs that satisfy one or more regions of operation or one or more specification criteria, (B) selecting a plurality of subsets of the initial designs based on a plurality of different techniques to establish a plurality of selected designs, (C) recombining some of the selected designs to generate a plurality of recombined designs, and (D) mutating some of the recombined designs to generate the new designs.

Claims (46)

1. A method for analog circuit design, comprising the steps of:

(A) evaluating an initial population comprising a plurality of initial designs of an analog circuit using a computer to determine to breed a plurality of new designs that either (i) satisfy one or more regions of operation or (ii) satisfy one or more specification criteria;

(B) selecting a plurality of subsets of said initial designs based on a plurality of first techniques and one or more second techniques to establish a plurality of selected designs, wherein a size of each subset selected by said first techniques and said second techniques is based on said determination to satisfy said regions of operation or said specification criteria;

(C) recombining some of said selected designs established by said first techniques to generate a plurality of recombined designs;

(D) mutating some of said recombined designs to generate a plurality of mutated designs;

(E) matching a plurality of circuit parameters of said mutated designs and said selected designs established by said second techniques to generate said new designs and

(F) generating a design file of at least one of said new designs, wherein a plurality of chips are fabricated using said design file.

2. The method according to claim 1 , wherein said first techniques to breed based on said regions of operation comprise (i) a best compatible region strategy and (ii) a tournament selection strategy.

3. The method according to claim 1 , wherein said first techniques to breed based on said specification criteria comprise (i) a best compatible specification strategy and (ii) a tournament selection strategy.

4. The method according to claim 1 , further comprising the step of:

searching said initial population with a correlation search technique to determine one or more of said new designs.

5. The method according to claim 1 , further comprising the step of:

searching said initial population with a local search technique to determine one or more of said new designs.

6. The method according to claim 1 , further comprising the step of:

searching said initial population with a genetically engineered search technique of said second techniques to determine one or more of said selected designs matched with said mutated designs.

7. The method according to claim 1 , wherein said recombining is based on all of a plurality of device parameters from a random portion of said selected designs.

8. The method according to claim 1 , wherein said mutating is based on all of a plurality of device parameters from a random portion of said selected designs.

9. The method according to claim 1 , further comprising the step of:

matching a plurality of devices in said initial designs where said devices have one or more common device parameters, wherein said evaluating is based on a result of said matching.

10. The method according to claim 1 , further comprising a non-transitory storage medium recording a computer program comprising the steps of claim 1 .

11. The method according to claim 1 , wherein said initial population is based on a distribution of circuit areas.

12. The method according to claim 1 , wherein a genetically engineered search technique of said second techniques comprises the steps of:

selecting one or more highest ranked designs of said initial designs that satisfy said specification criteria;

calculating a plurality of standard deviations and a plurality of median values in said highest ranked designs for each value of said circuit parameters and said specification criteria;

determining a plurality of smallest standard deviations of said circuit parameters in said highest ranked designs; and

generating one of said new designs having said values set to said media values.

13. The method according to claim 1 , wherein a best compatible region strategy of said first techniques comprises the steps of:

selecting a random design from said initial designs;

generating a plurality of idealistic designs based on (i) said initial designs and (ii) a best of said specification criteria or said regions of operation;

ranking said idealistic designs to determine a top design; and

generating one of said new designs by combining said random design and said top design.

14. An apparatus comprising:

a memory configured to store a plurality of program instructions to implement an analog circuit design; and

one or more processors coupled to said memory and configured to execute said program instructions, wherein said program instructions when executed cause said processor to perform the steps of:

(A) evaluating an initial population comprising a plurality of initial designs of an analog circuit to determine to breed a plurality of new designs that either (i) satisfy one or more regions of operation or (ii) satisfy one or more specification criteria;

(B) selecting a plurality of subsets of said initial designs based on a plurality of first techniques and one or more second techniques to establish a plurality of selected designs, wherein a size of each subset selected by said first techniques and said second techniques is based on said determination to satisfy said regions of operation or said specification criteria;

(C) recombining some of said selected designs established by said first techniques to generate a plurality of recombined designs;

(D) mutating some of said recombined designs to generate a plurality of mutated designs;

(E) matching a plurality of circuit parameters of said mutated designs and said selected designs established by said second techniques to generate said new designs and

(F) generating a design file of at least one of said new designs, wherein a plurality of chips are fabricated using said design file.

15. The apparatus according to claim 14 , wherein said first techniques to breed based on said regions of operation comprise (i) a best compatible region strategy and (ii) a tournament selection strategy.

16. The apparatus according to claim 14 , wherein said first techniques to breed based on said specification criteria comprise (i) a best compatible specification strategy and (ii) a tournament selection strategy.

17. The apparatus according to claim 14 , wherein said program instructions further comprise the step of:

searching said initial population with a correlation search technique to determine one or more of said new designs.

18. The apparatus according to claim 14 , wherein said program instructions further comprise the step of:

searching said initial population with a local search technique to determine one or more of said new designs.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2016
From: RAJAGOPALAN, SOWMYAN; YATES, CHRISTOPHER M.
To: THALIA DESIGN AUTOMATION LTD.
Reel/Frame 037735/0330 →
Continuity (2)
Provisional Application 62114189 · Feb 10, 2015
Related Publication 20160232268A1 · Aug 11, 2016