Power semiconductor device

1. A power semiconductor device having an active area, an interface area provided around a periphery of said active area, and an edge termination area provided around a periphery of said interface area, said power semiconductor device comprising:

a semiconductor substrate having a first surface and a second surface opposite to said first surface, said first surface and said second surface each being located across said active area, said interface area, and said edge termination area, said semiconductor substrate including

a drift region that is provided across said active area, said interface area, and said edge termination area and has a first conductivity type,

a collector region that is provided only in said active area, forms part of said second surface, and has a second conductivity type different from said first conductivity type, and

a buffer layer that has a portion located between said drift region and said collector region in said active area, has said first conductivity type, and has an impurity concentration higher than an impurity concentration in said drift region;

an emitter electrode that is provided in said active area and contacts said first surface of said semiconductor substrate; and

a collector electrode that is provided on said second surface of said semiconductor substrate and contacts said collector region, wherein

said active area has a MIS structural portion in which a MIS structural cell is disposed and a non-MIS structural portion in which no MIS structural cell is disposed,

said buffer layer and said collector electrode contact each other on said second surface of said semiconductor substrate in said non-MIS structural portion, and

said MIS structural portion includes two portions and the non-MIS structural portion is between the two portions of the MIS structural portion, and said collector electrode and said emitter electrode are electrically connected to said two MIS structural portions of the MIS structural cell.

2. The power semiconductor device according to claim 1 , wherein said collector region has an area accounting for greater than or equal to 55% and less than or equal to 70% of said second surface of said semiconductor substrate.

3. The power semiconductor device according to claim 1 , wherein said collector electrode on said second surface of said semiconductor substrate contacts said collector region in said active area and contacts said buffer layer in said interface area and said edge termination area.

4. The power semiconductor device according to claim 1 , wherein

said buffer layer is provided only in said active area among said active area, said interface area, and said edge termination area, and

said collector electrode on said second surface of said semiconductor substrate contacts said collector region in said active area and contacts said drift region in said interface area and said edge termination area.

5. The power semiconductor device according to claim 1 , wherein said semiconductor substrate includes a well region that is provided on said first surface, is at least partially included in said interface area, has an end portion on said first surface between said interface area and said edge termination area, and has said second conductivity type.

6. The power semiconductor device according to claim 5 , wherein

said first surface has an electrical path formed thereon, said electrical path connecting said emitter electrode to said end portion of said well region with a region of said second conductivity type,

said electrical path has a resistance region that is formed of said well region and has a width L, and

the width L is set so as to suppress a local temperature rise in one of both ends of said resistance region by sharing the temperature rise at said both ends during a breaking operation of said power semiconductor device.

7. The power semiconductor device according to claim 6 , wherein said L is greater than or equal to 100 μm.

8. The power semiconductor device according to claim 1 , wherein

each of said two portions of said MIS structural portion comprises a gate insulating film and a gate electrode that constitute said MIS structural cell, and

said non-MIS structural portion comprises an interlayer insulating film disposed on said first surface of said semiconductor substrate and a gate wiring portion disposed on said interlayer insulating film.

9. A power semiconductor device having an active area, an interface area provided around a periphery of said active area, and an edge termination area provided around a periphery of said interface area, said power semiconductor device comprising:

a semiconductor substrate having a first surface and a second surface opposite to said first surface, said first surface and said second surface each being located across said active area, said interface area, and said edge termination area, said semiconductor substrate including

a drift region that is provided across said active area, said interface area, and said edge termination area and has a first conductivity type, and

a well region that is provided on said first surface, is at least partially included in said interface area, has an end portion on said first surface between said interface area and said edge termination area, and has a second conductivity type different from said first conductivity type;

a first electrode that is provided in said active area and contacts said first surface of said semiconductor substrate, said first surface having an electrical path formed thereon, said electrical path connecting said first electrode to said end portion of said well region with a region of said second conductivity type, said electrical path having a resistance region that is formed of said well region and has a width L, the width L being greater than or equal to 100 μm to suppress a local temperature rise in one of both ends of said resistance region by sharing the temperature rise at said both ends during an operation of said power semiconductor device; and

a second electrode contacting said second surface of said semiconductor substrate.

10. The power semiconductor device according to claim 9 , wherein said first surface of said semiconductor substrate in said active area has an area S act ,

said resistance region on said first surface of said semiconductor substrate in said interface area has an area S abr , and

said area S abr is greater than or equal to 2% and less than or equal to 40% of the area S act .

11. The power semiconductor device according to claim 9 , wherein said semiconductor substrate includes:

a collector region that is provided only in said active area, forms part of said second surface, and has a second conductivity type different from said first conductivity type; and

a buffer layer that has a portion located between said drift region and said collector region in said active area, has said first conductivity type, and has an impurity concentration higher than an impurity concentration in said drift region.

12. The power semiconductor device according to claim 11 , wherein said second electrode on said second surface of said semiconductor substrate contacts said collector region in said active area and contacts said buffer layer in said interface area and said edge termination area.

13. The power semiconductor device according to claim 11 , wherein

said buffer layer is provided only in said active area among said active area, said interface area, and said edge termination area, and

said second electrode on said second surface of said semiconductor substrate contacts said collector region in said active area and contacts said drift region in said interface area and said edge termination area.

14. The power semiconductor device according to claim 11 , wherein

said active area has a MIS structural portion in which a MIS structural cell is disposed and a non-MIS structural portion in which no MIS structural cell is disposed, and

said buffer layer and said second electrode contact each other on said second surface of said semiconductor substrate in said non-MIS structural portion.

15. A power semiconductor device having an active area, an interface area provided around a periphery of said active area, and an edge termination area provided around a periphery of said interface area, said power semiconductor device comprising:

a semiconductor substrate having a first surface and a second surface opposite to said first surface, said first surface and said second surface each being located across said active area, said interface area, and said edge termination area, said semiconductor substrate including

a drift region that is provided across said active area, said interface area, and said edge termination area and has a first conductivity type,

a collector region that is provided only in said active area, forms part of said second surface, and has a second conductivity type different from said first conductivity type, and

a buffer layer that has a portion located between said drift region and said collector region in said active area, has said first conductivity type, and has an impurity concentration higher than an impurity concentration in said drift region;

an emitter electrode that is provided in said active area and contacts said first surface of said semiconductor substrate; and

a collector electrode that is provided on said second surface of said semiconductor substrate and contacts said collector region, wherein

said semiconductor substrate includes a well region that is provided on said first surface, is at least partially included in said interface area, has an end portion on said first surface between said interface area and said edge termination area, and has said second conductivity type,

in said interface area, a contact at the same potential as the emitter electrode to said well region is not provided, and

a width of an electrical path from a connection of the emitter electrode to the well region in the active area to the end portion of the well region is greater than or equal to 100 μm.