Separation of alpha emitting species from plating baths
View Patent ↗A non alpha controlled Tin including Tin and a trace amount of Polonium is utilized as a plating anode to selectively plate Tin upon a plating cathode. Tin may be selectively plated by pulse plating the non alpha controlled Tin with current control to suppress plating of Polonium upon the plating cathode. Tin may also be selectively plated by pulse plating the non alpha controlled Tin with potential control to suppress plating of Polonium upon the plating cathode. Tin may also be selectively plated by pulse and reverse plating to plate out Polonium upon a filtering cathode. Tin may also be selectively plated by plating out Polonium upon a filtering cathode within a concentrate. Tin may also be selectively plated by plating out purified Tin upon a filtering cathode, separating the purified Tin from the filtering cathode, and utilizing the purified Tin to plate Tin upon the plating cathode.
1. A plating method comprising:
creating a circuit between a plating anode and a plating cathode, the plating anode comprising Tin (Sn) and a trace amount of Polonium (Po) and the plating cathode comprising a semiconductor wafer, wherein the plating anode is formed with no prior electrolytic purification process;
utilizing the plating anode as a consumable anode to dissolve tin and the trace amount of polonium into a plating bath into which the plating anode and the plating cathode are immersed; and
selectively plating Sn upon the semiconductor wafer from the plating bath.
2. The method of claim 1 , further comprising:
suppressing plating of Po upon the semiconductor wafer.
3. The method of claim 2 , wherein suppressing plating of Po upon the semiconductor wafer further comprises:
increasing agitation of the plating bath and increasing the concentration of Sn ions near the semiconductor wafer.
4. The method of claim 3 , wherein controlled current pulses through the circuit increases the concentration of Sn ions near the semiconductor wafer.
5. The method of claim 2 , wherein suppressing plating of Po upon the semiconductor wafer further comprises:
controlling potential across the circuit to a plating potential that which Po does not plate.
6. The method of claim 5 , further comprising:
measuring a reference potential within the plating bath at a plating surface of the semiconductor wafer.
7. The method of claim 2 , wherein suppressing plating of Po reduces the alpha particle emission rate of the semiconductor wafer.