Display device of improved display quality and reduced power consumption
The disclosed display device of improved display quality and reduced power consumption includes a display unit including pixels coupled to gate lines and data lines, a gate driving unit for outputting a gate signal to the gate lines, a data driving unit for outputting a data signal to the data lines, a voltage supply unit for supplying to the gate driving unit a gate-on voltage to generate the gate signal a gate-off voltage, and a kickback compensation voltage having a voltage level varied at a section of time of the gate-on voltage, and a display mode control unit for controlling the voltage supply unit to supply the kickback compensation voltage during a first display mode for displaying an image on an entire area of the display unit, and to block supply of the kickback compensation voltage during a second display mode for displaying an image on only a partial area.
1. A display device, comprising;
a display unit comprising a plurality of pixels coupled to gate lines and data lines;
a gate driving unit for outputting a gate signal to the gate lines;
a data driving unit for outputting a data signal to the data lines;
a voltage supply unit for supplying to the gate driving unit:
a gate-on voltage to generate the gate signal;
a gate-off voltage; and
a kickback compensation voltage having a voltage level varied at a section of time of the gate-on voltage; and
a display mode control unit for controlling the voltage supply unit to supply the kickback compensation voltage during a first display mode for displaying an image on an entire area of the display unit, and to block supply of the kickback compensation voltage during a second display mode for displaying an image on only a partial area of the display unit.
2. The display device of claim 1 , wherein the display mode control unit is configured to generate a kickback compensation control signal for controlling supply of the kickback compensation voltage.
3. The display device of claim 2 , wherein a voltage level of the kickback compensation voltage corresponds to a kickback voltage generated during the first display mode.
4. The display device of claim 3 , wherein the gate signal has a falling edge between the gate-on voltage and the gate-off voltage, the falling edge comprising a slice section due to the kickback compensation voltage.
5. The display device of claim 1 , further comprising a memory for storing information of the kickback compensation voltage.
6. The display device of claim 1 , wherein the voltage supply unit is configured to supply a common voltage to the display unit, and
wherein the display mode control unit is configured to generate a common voltage control signal for controlling the voltage supply unit to supply a first common voltage as the common voltage during the first display mode, and to supply a second common voltage, which has a lower voltage level than the first common voltage, as the common voltage during the second display mode.
7. The display device of claim 6 , wherein a voltage level of the second common voltage corresponds to a kickback voltage generated during the second display mode.
8. The display device of claim 7 , wherein a voltage level of the second common voltage is between a positive data voltage and a negative data voltage.
9. The display device of claim 1 , wherein the display mode control unit is configured to generate a gate-on voltage control signal for controlling the voltage supply unit to supply a first gate-on voltage as the gate-on voltage during the first display mode, and to supply a second gate-on voltage, which has a lower voltage level than the first gate-on voltage, as the gate-on voltage during the second display mode.
10. The display device of claim 9 , wherein the second gate-on voltage corresponds to a kickback voltage generated during the second display mode.
11. The display device of claim 10 , wherein the second gate-on voltage is between the first gate-on voltage and the gate-off voltage.
12. The display device of claim 1 , wherein the display mode control unit is configured to generate a gate timing control signal for controlling the gate driving unit to supply the gate signal at a first output time during the first display mode, and to supply the gate signal at a second output time, which is before the first output time, during the second display mode.
13. The display device of claim 12 , wherein the second output time corresponds to a gate delay margin generated during the second display mode.
14. The display device of claim 1 , wherein the data driving unit is configured to be operated in an inverse operation manner by inverting a voltage polarity of the data signal.