Semiconductor device having field insulation layer between two fins
Semiconductor devices are provided. The semiconductor device includes a first fin and a second fin on a substrate and a field insulation layer between the first fin and the second fin. The field insulation layer include a first insulation layer and a second insulation layer on the first insulation layer and connected to the first insulation layer. The second insulation layer is wider than the first insulation layer. A ratio of a top width to a bottom width of each of the first fin and the second fin exceeds 0.5.
1. A semiconductor device, comprising:
a first fin and a second fin on a substrate; and
a field insulation layer between the first fin and the second fin, and including a first insulation layer and a second insulation layer on the first insulation layer and connected to the first insulation layer, the second insulation layer having a width wider than a width of the first insulation layer,
wherein a ratio of a top width to a bottom width of each of the first fin and the second fin exceeds 0.5, and
wherein the second insulation layer includes a bottom surface having a second width, and a top surface facing the bottom surface and having a first width, and the second width being wider than the first width.
2. The semiconductor device as claimed in claim 1 , wherein the second insulation layer includes a curved sidewall connecting the top surface and the bottom surface.
3. The semiconductor device as claimed in claim 1 , further comprising a gate formed on the first fin, and a dummy gate formed on the field insulation layer.
4. The semiconductor device as claimed in claim 3 , further comprising an elevated source/drain formed in the first fin between the gate and the dummy gate.
5. The semiconductor device as claimed in claim 4 , wherein the second insulation layer contacts the source/drain.
6. The semiconductor device as claimed in claim 5 , wherein a part of the source/drain is disposed beneath the second insulation layer.
7. The semiconductor device as claimed in claim 1 , wherein a top surface of the second insulation layer and a top surface of the first fin are disposed on a same plane.
8. A semiconductor device, comprising:
a first fin and a second fin protruding on a substrate and including respective longer sides and shorter sides, the shorter side of the first fin and the shorter side of the second fin being spaced apart from each other to face each other;
a field insulation layer extending between the shorter side of the first fin and the shorter side of the second fin;
a gate extending on the first fin to intersect the first fin;
a dummy gate on the field insulation layer; and
a source/drain in the first fin between the gate and the dummy gate,
wherein each of the first fin and the second fin has a ratio of a top width to a bottom width measured along the shorter side of each of the first fin and the second fin exceeds 0.5,
wherein the field insulation layer includes a first insulation layer and a second insulation layer formed on the first insulation layer and having a width wider than a width of the first insulation layer, and
wherein the second insulation layer includes a bottom surface having a second width, and a top surface facing the bottom surface and having a first width, and the second width is greater than the first width.
9. The semiconductor device as claimed in claim 8 , wherein the second insulation layer includes a curved sidewall connecting the top surface and the bottom surface.
10. The semiconductor device as claimed in claim 8 , wherein a part of the source/drain is disposed beneath the second insulation layer.
11. The semiconductor device as claimed in claim 8 , wherein the second insulation layer contacts the source/drain.
12. A semiconductor device, comprising:
a first fin and a second fin protruding from a substrate and including respective longer sides and shorter sides, the shorter side of the first fin and the shorter side of the second fin being spaced apart from each other to face each other;
a field insulation layer between the shorter side of the first fin and the shorter side of the second fin, the field insulation layer including a first insulation layer and a second insulation layer on the first insulation layer;
a gate on the first fin to intersect the first fin;
a dummy gate on the field insulation layer; and
a source/drain in the first fin between the gate and the dummy gate,
wherein the second insulation layer is wider than the first insulation layer and a portion of the source/drain is below the second insulation layer, and
wherein the second insulation layer includes a bottom surface having a second width, and a top surface facing the bottom surface and having a first width, and the second width being greater than the first width.
13. The semiconductor device as claimed in claim 12 , wherein an upper surface of the second insulation layer is wider than the dummy gate.
14. The semiconductor device as claimed in claim 12 , wherein an upper surface of the second insulation layer is wider than the first fin.
15. The semiconductor device as claimed in claim 12 , wherein the first fin and the second fin contact the first insulation layer.
16. The semiconductor device as claimed in claim 12 , wherein a portion of the first insulation layer extends beyond the shorter sides of the first and second fins.