IP Library › Granted Patent US 10,033,361

Granted Patent B2

US 10,033,361 · App. 15/387,216 · Granted Jul 24, 2018

Level-shift circuit, driver IC, and electronic device

Inventors: Wataru Uesugi (Kanagawa, JP); Takeshi Osada (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H03K3/356182 G09G3/3648 G09G3/3696 H01L27/1225 G09G2300/0408 G09G2300/0871 G09G2310/0286

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Quick Facts

Patent No.: US 10,033,361
App. No.: 15/387,216
Granted: Jul 24, 2018
Kind: B2

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Abstract

A level-shift circuit that operates stably is provided. The level-shift circuit has a function of boosting a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage. The level-shift circuit includes first to eighth transistors. Gates of the third and seventh transistors are electrically connected to a wiring for transmitting a third signal for controlling the amounts of current flowing into one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor.

Claims (128)

1. A level-shift circuit comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor are each a p-channel transistor,

wherein the fourth transistor and the eighth transistor are each an n-channel transistor,

wherein the level-shift circuit is configured to boost a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage,

wherein one of a source and a drain of the first transistor is electrically connected to a wiring for transmitting the third voltage,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and a gate of the fifth transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a wiring for transmitting the second voltage,

wherein one of a source and a drain of the fifth transistor is electrically connected to the wiring for transmitting the third voltage,

wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor and a gate of the first transistor,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the wiring for transmitting the second voltage,

wherein a gate of the second transistor and a gate of the fourth transistor are electrically connected to a wiring for transmitting the first signal,

wherein a gate of the sixth transistor and a gate of the eighth transistor are electrically connected to a wiring for transmitting an inverted signal of the first signal,

wherein a gate of the third transistor and a gate of the seventh transistor are electrically connected to a wiring for transmitting a third signal that controls amounts of current flowing into the one of the source and the drain of the first transistor, the one of the source and the drain of the second transistor, the one of the source and the drain of the fifth transistor, and the one of the source and the drain of the sixth transistor, and

wherein a wiring for transmitting the second signal is electrically connected to the other of the source and the drain of the seventh transistor, the one of the source and the drain of the eighth transistor, and the gate of the first transistor.

2. The level-shift circuit according to claim 1 ,

wherein the fourth transistor and the eighth transistor each comprise a semiconductor layer where a channel is formed, and

wherein the semiconductor layer comprises an oxide semiconductor.

3. The level-shift circuit according to claim 1 , wherein at least one of the fourth transistor and the eighth transistor comprises a back gate.

4. The level-shift circuit according to claim 1 , wherein the third transistor and the seventh transistor are each a p-channel transistor.

5. The level-shift circuit according to claim 1 ,

wherein the third transistor and the seventh transistor are each an n-channel transistor comprising a semiconductor layer where a channel is formed, and

wherein the semiconductor layer comprises an oxide semiconductor.

6. A driver IC comprising:

the level-shift circuit according to claim 1 ; and

at least one of a shift register, a data latch, a pass transistor logic, a voltage generator circuit, and an amplifier.

7. An electronic device comprising:

the level-shift circuit according to claim 1 ; and

a display portion.

8. A level-shift circuit comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a first input terminal; and

a first output terminal,

wherein a constant voltage is applied to a gate of the first transistor,

wherein a gate of the second transistor is electrically connected to the first input terminal,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the third transistor,

wherein one of a source and a drain of the second transistor is directly connected to the gate of the third transistor,

wherein the other of the source and the drain of the second transistor is directly connected to a first wiring,

wherein one of a source and a drain of the third transistor is electrically connected to the first output terminal,

wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the first output terminal,

wherein the other of the source and the drain of the fifth transistor is directly connected to the first wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a second wiring, and

wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring.

9. The level-shift circuit according to claim 8 ,

wherein a signal having an amplitude voltage between a first voltage and a second voltage is input to the first input terminal,

wherein the first wiring is configured to transmit the second voltage,

wherein the second wiring is configured to transmit a third voltage, and

wherein a voltage difference between the third voltage and the second voltage is larger than a voltage difference between the first voltage and the second voltage, and

wherein the constant voltage is between the first voltage and the third voltage.

10. The level-shift circuit according to claim 9 , further comprising:

a sixth transistor;

a seventh transistor;

an eighth transistor;

a second input terminal; and

s second output terminal,

wherein a gate of the sixth transistor is electrically connected to the first input terminal,

wherein the one of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor though the sixth transistor,

wherein the one of the source and the drain of the second transistor is electrically connected to the second output terminal,

wherein a gate of the fifth transistor is electrically connected to the second input terminal,

wherein the constant voltage is applied to a gate of the seventh transistor,

wherein a gate of the eighth transistor is electrically connected to the second input terminal, and

wherein the one of the source and the drain of the third transistor is electrically connected to the first output terminal through the seventh transistor and the eighth transistor.

11. The level-shift circuit according to claim 8 ,

wherein the first transistor, the third transistor, and the fourth transistor are each a p-channel transistor, and

wherein the second transistor and the fifth transistor are each an n-channel transistor.

12. The level-shift circuit according to claim 11 ,

wherein the n-channel transistor comprises a semiconductor layer where a channel is formed, and

wherein the semiconductor layer comprises an oxide semiconductor.

13. A level-shift circuit comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor;

an eighth transistor;

a first terminal for transmitting a signal;

a second terminal;

a third terminal for transmitting a constant voltage;

a fourth terminal for transmitting an inverted signal;

a fifth terminal; and

a sixth terminal,

wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor are each a p-channel transistor,

wherein the fourth transistor and the eighth transistor are each an n-channel transistor,

wherein one of a source and a drain of the first transistor is electrically connected to the fifth terminal,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and a gate of the fifth transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the sixth terminal,

wherein one of a source and a drain of the fifth transistor is electrically connected to the fifth terminal,

wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor and a gate of the first transistor,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the sixth terminal,

wherein a gate of the second transistor and a gate of the fourth transistor are electrically connected to the first terminal,

wherein a gate of the sixth transistor and a gate of the eighth transistor are electrically connected to the fourth terminal,

wherein a gate of the third transistor and a gate of the seventh transistor are electrically connected to the third terminal, and

wherein the second terminal is electrically connected to the other of the source and the drain of the seventh transistor, the one of the source and the drain of the eighth transistor, and the gate of the first transistor.

14. The level-shift circuit according to claim 13 ,

wherein the fourth transistor and the eighth transistor each comprise a semiconductor layer where a channel is formed, and

wherein the semiconductor layer comprises an oxide semiconductor.

15. The level-shift circuit according to claim 14 ,

the oxide semiconductor includes at least one of indium and gallium.

16. The level-shift circuit according to claim 14 , wherein the fourth transistor and the eighth transistor are over the first transistor, the second transistor, the fifth transistor, and the sixth transistor with an insulator therebetween.

17. The level-shift circuit according to claim 13 , wherein at least one of the fourth transistor and the eighth transistor comprises a back gate.

18. The level-shift circuit according to claim 13 , wherein the third transistor and the seventh transistor are each a p-channel transistor.

19. The level-shift circuit according to claim 13 ,

wherein the third transistor and the seventh transistor are each an n-channel transistor comprising a semiconductor layer where a channel is formed, and

wherein the semiconductor layer comprises an oxide semiconductor.

20. The level-shift circuit according to claim 19 ,

wherein the oxide semiconductor includes at least one of indium and gallium.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017

From: UESUGI, WATARU; OSADA, TAKESHI

To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Reel/Frame 041259/0088 →

Priority Claims (1)

JP 2015-255855 · Dec 28, 2015 · national

Continuity (1)

Related Publication 20170187360A1 · Jun 29, 2017