Multi-chip structure and method of forming same
A device includes a redistribution layer over a molding compound layer, a first chip over the fan-out structure, wherein the first chip comprise a plurality of first through vias connected to the redistribution layer and a second chip over the first chip, the second chip being connected to the first chip through a plurality of bumps, wherein the first chip and the second chip are in the molding compound layer, and wherein a center line of the first chip is not vertically aligned with a center line of the second chip.
1. A device comprising:
a fan-out structure comprising a redistribution layer over a molding compound layer;
a first chip over the fan-out structure, wherein the first chip comprise a plurality of first through vias connected to the redistribution layer; and
a second chip over the first chip, the second chip being connected to the first chip through a plurality of bumps, wherein the first chip and the second chip are in the molding compound layer, and wherein a center line of the first chip is not vertically aligned with a center line of the second chip, wherein a sidewall of the first chip or a sidewall of the second chip is exposed outside the molding compound layer.
2. The device of claim 1 , further comprising:
a dielectric layer over the redistribution layer;
an under bump metallization structure over the dielectric layer; and
a solder ball over the under bump metallization structure.
3. The device of claim 1 , wherein:
the second chip comprises a plurality of memory dies stacked together; and
the first chip comprises a plurality of logic circuits.
4. The device of claim 1 , wherein:
a first sidewall of the first chip is exposed outside the molding compound layer;
a second sidewall of the first chip is covered by the molding compound layer;
a first sidewall of the second chip is covered by the molding compound layer; and
a second sidewall of the second chip is exposed outside the molding compound layer.
5. The device of claim 1 , wherein:
a first sidewall and a second sidewall of the first chip are covered by the molding compound layer;
a first sidewall of the second chip is covered by the molding compound layer; and
a second sidewall of the second chip is exposed outside the molding compound layer.
6. The device of claim 1 , wherein:
a first sidewall of the first chip is exposed outside the molding compound layer;
a second sidewall of the first chip is covered by the molding compound layer; and
a first sidewall and a second sidewall of the second chip are covered by the molding compound layer.
7. The device of claim 1 , wherein:
a first side of the second chip is connected to the first chip through the plurality of bumps.
8. The device of claim 1 , wherein:
the redistribution layer extends beyond a first sidewall and a second sidewall of the first chip.
9. The device of claim 7 , wherein:
a surface of a second side of the second chip is exposed outside the molding compound layer.
10. A device comprising:
a first chip and a second chip stacked together to form a multi-chip structure, wherein the first chip and the second chip are in an encapsulation layer, and wherein there is a separation between a center line of the first chip and a center line of the second chip;
a redistribution layer on a surface of a first side of the encapsulation layer, wherein the first chip is in direct contact with the redistribution layer, and a non-bonding surface of the second chip is exposed at a second side of the encapsulation layer; and
a plurality of conductive bumps over the redistribution layer.
11. The device of claim 10 , further comprising:
a dielectric layer over the redistribution layer; and
a plurality of under bump metallization structures between the dielectric layer and the plurality of conductive bumps.
12. The device of claim 10 , wherein:
at least one sidewall of the first chip is exposed outside the encapsulation layer; and
at least one sidewall of the second chip is exposed outside the encapsulation layer.
13. The device of claim 10 , wherein:
a width of the second chip is greater than a width of the first chip.
14. The device of claim 10 , wherein:
a sidewall of the first chip is exposed outside the encapsulation layer; and
two sidewalls of the second chip are covered by the encapsulation layer.
15. The device of claim 10 , wherein:
two sidewalls of the first chip are covered by the encapsulation layer; and
a sidewall of the second chip is exposed outside the encapsulation layer.
16. A method comprising:
mounting a second chip on a first chip, and wherein a center line of the first chip is not vertically aligned with a center line of the second chip;
forming a molding compound layer over the first chip and the second chip, wherein the first chip and the second chip are embedded in the molding compound layer;
grinding the molding compound layer until a surface of the second chip is exposed;
forming a redistribution layer on the surface of the second chip; and
forming a plurality of bumps over the redistribution layer.
17. The method of claim 16 , wherein:
the redistribution layer extends beyond at least one sidewall of the second chip.
18. The method of claim 16 , further comprising:
applying a reflow process to the first chip and the second chip so that the second chip is bonded on the first chip through a plurality of conductive bumps formed between the first chip and the second chip.
19. The method of claim 16 , wherein:
the first chip is a memory chip; and
the second chip is a processor chip.
20. The method of claim 16 , further comprising:
depositing a dielectric layer over the redistribution layer;
forming a plurality of under bump metallization structures in the dielectric layer; and
forming the plurality of bumps over the plurality of under bump metallization structures.