Semiconductor device
A semiconductor device with improved electrical characteristics is provided. A semiconductor device with improved field effect mobility is provided. A semiconductor device in which the field-effect mobility is not lowered even at high temperatures is provided. A semiconductor device which can be formed at low temperatures is provided. A semiconductor device with improved productivity can be provided. In the semiconductor device, there is a range of a gate voltage where the field-effect mobility increases as the temperature increases within a range of the gate voltage from 0 V to 10 V. For example, such a range of a gate voltage exists at temperatures ranging from a room temperature (25° C.) to 120° C. In the semiconductor device, the off-state current is kept extremely low (lower than or equal to the detection limit of a measurement device) within the above temperature range.
1. A semiconductor device comprising:
a transistor comprising a semiconductor layer,
wherein the semiconductor layer comprises an oxide semiconductor,
wherein the semiconductor layer is a stacked-layer structure,
wherein the semiconductor layer comprises In, M and Zn,
wherein M is Al, Ga, Y, or Sn,
wherein field-effect mobility of the transistor increases as a temperature increases within a range of a first gate voltage to a second voltage, and
wherein the first gate voltage is equal to or higher than 0 V and the second gate voltage is equal to or lower than 10 V.
2. The semiconductor device according to claim 1 , wherein the field-effect mobility increases continuously as a temperature increases within a temperature range of 25° C. to 120° C.
3. The semiconductor device according to claim 1 , wherein a channel length is preferably less than or equal to 3 μm.
4. The semiconductor device according to claim 1 , wherein the field-effect mobility of the transistor is greater than or equal to 10 cm 2 /V s within a range of a third gate voltage to a fourth gate voltage at temperatures ranging from 25° C. to 120° C., and
wherein the third gate voltage is equal to or higher than 2 V and the fourth gate voltage is equal to or lower than 10 V.
5. The semiconductor device according to claim 1 , wherein a drain current of the transistor in an off state is preferably lower than 5×10 −12 A at temperatures ranging from 25° C. to 120° C.
6. The semiconductor device according to claim 1 , wherein the semiconductor layer comprises a non-single-crystal region.
7. The semiconductor device according to claim 6 , wherein the semiconductor layer preferably comprises a first crystal part in which a c-axis is aligned in a thickness direction.
8. The semiconductor device according to claim 6 , wherein the semiconductor layer comprises a second crystal part with a size less than or equal to 10 nm which does not have orientation.
9. The semiconductor device according to claim 6 , wherein the semiconductor layer comprises an amorphous region.
10. The semiconductor device according to claim 1 , wherein the semiconductor layer comprises a region in which a proportion of In is greater than 33% and less than or equal to 60% is preferably included when the sum of the proportions of In, M, and Zn is defined as 1.
11. A semiconductor device comprising:
a transistor comprising:
a semiconductor layer;
a first conductive layer;
a second conductive layer;
a third conductive layer;
a fourth conductive layer;
a first insulating layer;
a second insulating layer; and
a third insulating layer,
wherein the first conductive layer is provided over a formation surface,
wherein the first insulating layer covering the first conductive layer is provided,
wherein the semiconductor layer overlapping with the first conductive layer is provided over the first insulating layer,
wherein the second insulating layer and the second conductive layer are stacked over the semiconductor layer,
wherein the third insulating layer is provided to cover the semiconductor layer and the second conductive layer,
wherein the third conductive layer and the fourth conductive layer are provided apart from each other over the third insulating layer,
wherein the third conductive layer and the fourth conductive layer are provided in contact with regions of the semiconductor layer not overlapping with the second conductive layer, through openings provided in the third insulating layer,
wherein the first conductive layer and the second conductive layer are electrically connected to each other and function as gates,
wherein the semiconductor layer comprises an oxide semiconductor,
wherein the semiconductor layer is a stacked-layer structure,
wherein the semiconductor layer comprises In, M and Zn,
wherein M is Al, Ga, Y, or Sn,
wherein field-effect mobility of the transistor increases as a temperature increases within a range of a first gate voltage to a second voltage, and
wherein the first gate voltage is equal to or higher than 0 V and the second gate voltage is equal to or lower than 10 V.
12. The semiconductor device according to claim 11 , wherein the field-effect mobility increases continuously as a temperature increases within a temperature range of 25° C. to 120° C.
13. The semiconductor device according to claim 11 , wherein a channel length is preferably less than or equal to 3 μm.
14. The semiconductor device according to claim 11 ,
wherein the field-effect mobility of the transistor is greater than or equal to 10 cm 2 /V s within a range of a third gate voltage to a fourth gate voltage at temperatures ranging from 25° C. to 120° C., and
wherein the third gate voltage is equal to or higher than 2 V and the fourth gate voltage is equal to or lower than 10 V.
15. The semiconductor device according to claim 11 , wherein a drain current of the transistor in an off state is preferably lower than 5×10 −12 A at temperatures ranging from 25° C. to 120° C.
16. A semiconductor device comprising:
a transistor comprising:
a semiconductor layer;
a first conductive layer;
a second conductive layer;
a third conductive layer;
a fourth conductive layer;
a first insulating layer; and
a second insulating layer,
wherein the first conductive layer is provided over a formation surface,
wherein the first insulating layer covering the first conductive layer is provided,
wherein the semiconductor layer overlapping with the first conductive layer is provided over the first insulating layer,
wherein the third conductive layer and the fourth conductive layer are provided apart from each other to be in contact with a top surface of the semiconductor layer,
wherein the second insulating layer covering the semiconductor layer, the third conductive layer, and the fourth conductive layer is provided,
wherein the second conductive layer overlapping with a region of the semiconductor layer where the third conductive layer and the fourth conductive layer are apart from each other is provided over the second insulating layer,
wherein the first conductive layer and the second conductive layer are electrically connected with each other and function as gates,
wherein the semiconductor layer comprises an oxide semiconductor,
wherein the semiconductor layer is a stacked-layer structure,
wherein the semiconductor layer comprises In, M and Zn,
wherein M is Al, Ga, Y, or Sn,
wherein field-effect mobility of the transistor increases as a temperature increases within a range of a first gate voltage to a second voltage, and
wherein the first gate voltage is equal to or higher than 0 V and the second gate voltage is equal to or lower than 10 V.
17. The semiconductor device according to claim 16 , wherein the field-effect mobility increases continuously as a temperature increases within a temperature range of 25° C. to 120° C.
18. The semiconductor device according to claim 16 , wherein a channel length is preferably less than or equal to 3 μm.
19. The semiconductor device according to claim 16 ,
wherein the field-effect mobility of the transistor is greater than or equal to 10 cm 2 /V s within a range of a third gate voltage to a fourth gate voltage at temperatures ranging from 25° C. to 120° C., and
wherein the third gate voltage is equal to or higher than 2 V and the fourth gate voltage is equal to or lower than 10 V.
20. The semiconductor device according to claim 16 , wherein a drain current of the transistor in an off state is preferably lower than 5×10 −12 A at temperatures ranging from 25° C. to 120° C.
21. The semiconductor device according to claim 1 , wherein the semiconductor layer is formed over a substrate, the substrate is not heated.
22. The semiconductor device according to claim 11 , wherein the semiconductor layer is formed over a substrate, the substrate is not heated.
23. The semiconductor device according to claim 16 , wherein the semiconductor layer is formed over a substrate, the substrate is not heated.