IP Library › Granted Patent US 10,042,131
Granted Patent B1
US 10,042,131 · App. 15/480,277 · Granted Aug 7, 2018

Architecture for silicon photonics enabling wafer probe and test

Inventor: Austin H. Lesea (Los Gatos, CA)
Assignee: XILINX, INC.
G02B6/4227G02B6/12004G02B6/124G02B6/125G02B6/13G02B6/4225G02B2006/1215G02B2006/12061G02B2006/12147
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,042,131
App. No.
15/480,277
Filed
Apr 5, 2017
Granted
Aug 7, 2018
Kind
B1
Art Unit
2883
USPC
385/14
Abstract

Embodiments herein describe techniques for testing or aligning optical components in a photonic chip using a grating coupler. In one embodiment, the photonic chip may include an edge coupler and a grating coupler for optically coupling the photonic chip to external fiber optic cables. The edge coupler may be disposed on a side or edge of the photonic chip while the grating coupler is located on a top or side of the photonic chip. During fabrication, the edge coupler may be inaccessible. Instead of using the edge coupler to test the photonic chip, a testing apparatus can use the grating coupler along with a splitter to transfer optical test signals between an optical component in the photonic chip (e.g., a modulator or detector) and a test probe optically coupled to the grating coupler.

Claims (38)

1. A photonic semiconductor chip, comprising:

an edge coupler directly coupled to a first end of a first waveguide, wherein the edge coupler is arranged to transfer first optical signals along a side plane of the photonic semiconductor chip, wherein the edge coupler is configured to change a mode size as the first optical signals propagate through the edge coupler;

a splitter directly coupled to (i) a second end of the first waveguide, (ii) a first end of a second waveguide, and (iii) a first end of a third waveguide, wherein the splitter is configured to receive a first optical signal from one of the first, second, and third waveguides and transmit first and second attenuated portions of the first optical signal onto the remaining two of the first, second, and third waveguides;

a grating coupler directly coupled to a second end of the second waveguide, wherein the grating coupler is arranged to transfer second optical signals along a top plane of the photonic semiconductor chip that is perpendicular to the side plane; and

an optical component coupled to a second end of the third waveguide.

2. The photonic semiconductor chip of claim 1 , wherein the edge coupler is exposed on an external side surface of the photonic semiconductor chip and the grating coupler is exposed on an external top surface of the photonic semiconductor chip, wherein the side surface is perpendicular to the top surface.

3. The photonic semiconductor chip of claim 2 , wherein the optical component is connected via a conductive trace to a conductive pad disposed on the top surface.

4. The photonic semiconductor chip of claim 1 , wherein the first, second, and third waveguides have at least one dimension less than a micron, and wherein the first, second, and third waveguides are disposed on a common plane in the photonic semiconductor chip.

5. The photonic semiconductor chip of claim 4 , wherein the common plane is an interface between a top semiconductor surface layer of the photonic semiconductor chip and an insulation layer of the photonic semiconductor chip, wherein the first waveguide, the second waveguide, the third waveguide, the edge coupler, and the grating coupler are disposed on the insulation layer.

6. The photonic semiconductor chip of claim 1 , wherein the optical component is one of an optical detector and optical modulator.

7. The photonic semiconductor chip of claim 1 , further comprising a silicon-on-insulator (SOI) structure, wherein the first, second, and third waveguides are silicon waveguides disposed on an insulation layer in the SOI structure.

8. A method, comprising:

providing a photonic semiconductor chip comprising an edge coupler, a grating coupler, a splitter, and an optical component, wherein the edge coupler is directly coupled to a first end of a first waveguide, the splitter is directly coupled to (i) a second end of the first waveguide, (ii) a first end of a second waveguide, and (iii) a first end of a third waveguide, the grating coupler is directly coupled to a second end of the second waveguide, and the optical component is coupled to a second end of the third waveguide;

transferring an optical signal between a test probe and the grating coupler, wherein the edge coupler is arranged to transfer first optical signals along a side plane of the photonic semiconductor chip and the grating coupler is arranged to transfer second optical signals along a top plane of the photonic semiconductor chip that is perpendicular to the side plane; and

testing the functionality of the optical component based on transferring the optical signal.

9. The method of claim 8 , the method further comprising:

providing a wafer comprising the photonic semiconductor chip, wherein transferring the optical signal occurs when the photonic semiconductor chip is part of the wafer, wherein the wafer includes a plurality of photonic semiconductor chips.

10. The method of claim 9 , further comprising:

cutting the wafer to separate the photonic semiconductor chip from the plurality of photonic semiconductor chips thereby exposing the edge coupler on an external side surface of the photonic semiconductor chip.

11. The method of claim 10 , further comprising:

receiving light transmitted by an external carrying medium at the edge coupler;

measuring the received light at the grating coupler using the test probe; and

aligning the external carrying medium to the edge coupler based on the measured light.

12. The method of claim 10 , wherein the grating coupler is exposed on an external top surface of the photonic semiconductor chip, wherein the external side surface is perpendicular to the external top surface.

13. The method of claim 12 , wherein the optical component is connected via a conductive trace to a conductive pad disposed on the top surface.

14. The method of claim 9 , wherein the first, second, and third waveguides have at least one dimension less than a micron, and wherein the first, second, and third waveguides are disposed on a common plane in the photonic semiconductor chip.

15. A method, comprising:

providing a wafer comprising a plurality of photonic chips integrated into the wafer, wherein a first photonic chip of the plurality of photonic chips comprises a grating coupler, a splitter, a first optical component, and an edge coupler, wherein the grating coupler is directly coupled to a first end of a first waveguide, the splitter is directly coupled to (i) a second end of the first waveguide, (ii) a first end of a second waveguide, and (iii) a first end of a third waveguide, the first optical component is coupled to a second end of the second waveguide, and the the edge coupler is directly coupled to a second end of the third waveguide;

transferring an optical signal between a test probe and the grating coupler, wherein the grating coupler is arranged to transfer the optical signal along a top plane of the first photonic chip that is parallel to a common plane on which the first and second waveguides are disposed;

testing the functionality of the first optical component based on transferring the optical signal; and

cutting the wafer to separate the first photonic chip from the plurality of photonic chips.

16. The method of claim 15 , wherein the splitter is configured to receive a first optical signal from one of the first and second, and third waveguides and transmit first and second attenuated portions of the first optical signal onto the remaining two of the first, second, and third waveguides.

17. The method of claim 15 , wherein the first optical component is connected via a conductive trace to a conductive pad disposed on the top plane.

18. The method of claim 15 , wherein the first, second, and third waveguides have at least one dimension less than a micron, and wherein the first, second, and third waveguides are disposed on a common plane in the photonic chip.

19. The method of claim 15 , further comprising, after cutting the wafer:

checking the functionality of the first optical component by transferring a second optical signal between the grating coupler and the test probe.

20. The method of claim 15 , further comprising after cutting the wafer:

covering up the grating coupler with a non-transparent material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2017
From: LESEA, AUSTIN H.
To: XILINX, INC.
Reel/Frame 041866/0822 →
Cited By (16)
US 12,196,672 US 12,222,257 US 12,352,670 US 12,416,763 US 12,422,360 US 12,422,361 US 12,422,362 US 12,449,356 US 12,498,328 US 12,529,696 US 12,553,885 US 12,554,063 US 12,674,948 US 12,674,949 US 12,687,676 US 12,699,240