MOS capacitors for variable capacitor arrays and methods of forming the same

1. A capacitor structure comprising:

a substrate;

a first plurality of source/drain regions formed in said substrate; and

a first plurality of gates formed above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a channel between said each pair of source/drain regions, each source/drain region of said first plurality of source/drain regions formed between a pair of gates of said first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates;

wherein said substrate, said first plurality of source/drain regions and said first plurality of gates are interconnected to form a first capacitor.

2. The capacitor structure of claim 1 , wherein said substrate is a silicon-on-insulator substrate.

3. The capacitor structure of claim 1 , wherein said substrate includes a second plurality of source/drain regions and a second plurality of gates interconnected to form at least a second capacitor, at least said first capacitor and said second capacitor connected in an anti-series configuration.

4. The capacitor structure of claim 1 , wherein said substrate includes a second plurality of source/drain regions and a second plurality of gates, said first plurality of source/drain regions, said second plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form a variable capacitor cell of a variable capacitor array.

5. The capacitor structure of claim 4 , wherein the variable capacitor cell is part of an integrated circuit.

6. The capacitor structure of claim 1 , wherein said substrate includes at least a second plurality of source/drain regions and at least a second plurality of gates, at least said second plurality of source/drain regions and at least said second plurality of gates are interconnected to form a plurality of variable capacitor cells of a variable capacitor array.

7. The capacitor structure of claim 1 , wherein said substrate includes a second plurality of source/drain regions and a second plurality of gates, said first plurality of source/drain regions, said second plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form a variable capacitor cell of a variable capacitor array.

8. A method to form a plurality of capacitors comprising:

forming a first plurality of source/drain regions in a substrate;

forming a first plurality of gates above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a channel between said each pair of source/drain regions, each source/drain region of said first plurality of source/drain regions formed between a pair of gates of said first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates; and

forming connections between said first plurality of source/drain regions and said first plurality of gates to form a first capacitor.

9. The method of claim 8 , wherein said substrate is a silicon-on-insulator substrate.

10. The method of claim 8 , further comprising:

forming a second plurality of source/drain regions in said substrate;

forming a second plurality of gates above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a channel between said each pair of source/drain regions;

forming connections between said second plurality of source/drain regions and said second plurality of gates to form at least a second capacitor; and

forming connections between at least said first capacitor and said second capacitor to form one or more pairs of capacitors connected in an anti-series configuration.

11. The method of claim 8 , further comprising:

forming a second plurality of source/drain regions in said substrate;

forming a second plurality of gates above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a channel between said each pair of source/drain regions;

forming connections between said first plurality of source/drain regions, said first plurality of gates, said second plurality of source/drain regions, and said second plurality of gates to form a variable capacitor cell of a variable capacitor array.

12. The capacitor structure of claim 8 , further comprising:

forming a second plurality of source/drain regions in said substrate;

forming a second plurality of gates above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a channel between said each pair of source/drain regions;

forming connections between at least said second plurality of source/drain regions and said second plurality of gates to form a plurality of variable capacitor cells of a variable capacitor array.

13. An integrated circuit comprising:

a substrate;

a first plurality of source/drain regions formed in said substrate; and

a first plurality of gates formed above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a channel between said each pair of source/drain regions, each source/drain region of said first plurality of source/drain regions formed between a pair of gates of said first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates;

wherein said substrate, said first plurality of source/drain regions and said first plurality of gates are interconnected to form a first capacitor.

14. The integrated circuit of claim 13 , wherein said substrate is a silicon-on-insulator substrate.

15. The integrated circuit of claim 13 , wherein said substrate includes a second plurality of source/drain regions and a second plurality of gates interconnected to form at least a second capacitor, at least said first capacitor and said second capacitor connected in an anti-series configuration.

16. The integrated circuit of claim 13 , wherein said substrate includes a second plurality of source/drain regions and a second plurality of gates, said first plurality of source/drain regions, said second plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form a variable capacitor cell of a variable capacitor array.

17. The integrated circuit of claim 16 , further comprising a bias voltage generator configured to generate a bias voltage for each one of said plurality of variable capacitor cells of said variable capacitor array.

18. The integrated circuit of claim 17 , further comprising an interface configured to receive a control signal for said bias voltage generator used to adjust a value of said bias voltage for each one of said plurality of variable capacitor cells of said variable capacitor array.

19. The integrated circuit of claim 18 , wherein said interface is a Mobile Industry Processor Interface radio front end interface.

20. The integrated circuit of claim 13 , wherein said substrate includes at least a second plurality of source/drain regions and at least a second plurality of gates, at least said second plurality of source/drain regions and at least said second plurality of gates are interconnected to form a plurality of variable capacitor cells of a variable capacitor arrays.