Band selected clock data recovery circuit and associated method
A clock data recovery (CDR) circuit includes: a band select circuit, a low dropout regulator (LDO), a charge pump and a voltage-controlled oscillator (VCO), wherein the band select circuit is arranged to generate a digital signal according to at least a reference voltage; the LDO is arranged to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO; the charge pump is arranged to generate a control voltage according to at least a part of the digital signal; and the VCO is arranged to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO.
1. A clock data recovery (CDR) circuit, comprising:
a band select circuit, arranged to generate a digital signal according to at least a reference voltage;
a low dropout regulator (LDO), arranged to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO;
a charge pump, arranged to generate a control voltage according to at least a part of the digital signal; and
a voltage-controlled oscillator (VCO), arranged to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO.
2. The CDR circuit of claim 1 , wherein the LDO comprises:
a bias control circuit, arranged to receive at least a part of the digital signal to control the bias current passing through the amplifier of the LDO.
3. The CDR circuit of claim 1 , wherein the LDO receives a regulating ground voltage generated by the VCO to regulate the ground voltage.
4. The CDR circuit of claim 1 , wherein the VCO comprises:
a current generating circuit, arranged to receive the control voltage to generate a reference current; and
a control circuit, arranged to generate the bias current of the VCO according to the reference current and the at least a part of the digital signal.
5. The CDR circuit of claim 4 , wherein the VCO adjusts the operating band of the CDR circuit by receiving the at least a part of the digital signal to adjust the bias current of the VCO by:
receiving the at least a part of the digital signal by the control circuit to generate the bias current according to the reference current and the at least a part of the digital signal in order to adjust the operating band of the CDR circuit.
6. The CDR circuit of claim 5 , wherein the adjusted operating band of the CDR circuit corresponds to one of a plurality of ranges of the clock signal frequency.
7. The CDR circuit of claim 4 , wherein the VCO adjusts the operating band of the CDR circuit by receiving the at least a part of the digital signal to adjust the bias current of the VCO by:
receiving the at least a part of the digital signal by the charge pump to generate and output the control voltage to the current generating circuit of the VCO;
generating the reference current according to the control voltage, and outputting the reference current to the control circuit;
generating the bias current according to the reference current; and
adjusting the operating band of the CDR circuit according to the bias current.
8. The CDR circuit of claim 1 , further comprising:
a low pass filter (LPF) coupled between the charge pump and the VCO.
9. A clock data recovery (CDR) method for a CDR circuit, comprising:
generating a digital signal according to at least a reference voltage; and
utilizing a low dropout regulator (LDO) to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO;
generating a control voltage according to at least a part of the digital signal; and
utilizing a voltage-controlled oscillator (VCO) to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO;
wherein the LDO receives a regulating ground voltage generated by the VCO to regulate the ground voltage.
10. The CDR method of claim 9 , further comprising:
receiving the control voltage to generate a reference current; and
generating the bias current of the VCO according to the reference current and the at least a part of the digital signal.
11. The CDR method of claim 9 , wherein the step of the VCO adjusting the operating band of the CDR circuit by receiving the at least a part of the digital signal to adjust the bias current of the VCO comprises:
receiving the at least a part of the digital signal to generate the bias current according to a reference current and the at least a part of the digital signal in order to adjust the operating band of the CDR circuit.
12. The CDR method of claim 11 , wherein the adjusted operating band of the CDR circuit corresponds to one of a plurality of ranges of the clock signal frequency.
13. The CDR method of claim 9 , wherein the step of the VCO adjusting the operating band of the CDR circuit by receiving the at least a part of the digital signal to adjust the bias current of the VCO comprises:
receiving the at least a part of the digital signal to generate and output the control voltage to the VCO;
generating a reference current according to the control voltage;
generating the bias current according to the reference current; and
adjusting the operating band of the CDR circuit according to the bias current.