IP Library › Granted Patent US 10,049,619

Granted Patent B2

US 10,049,619 · App. 15/342,530 · Granted Aug 14, 2018

Display device and method of driving the same

Inventors: Geun Hyuk Choi (Yongin-si, KR); Sang Hyun Lee (Yongin-si, KR); Hyo Chul Lee (Yongin-si, KR); Jae Ho Choi (Yongin-si, KR); Hyun Seok Hong (Yongin-si, KR)

Assignee: SAMSUNG DISPLAY CO., LTD.

G09G3/3266 G09G3/3291 G09G2310/0286 G09G2310/08

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Quick Facts

Patent No.: US 10,049,619
App. No.: 15/342,530
Granted: Aug 14, 2018
Kind: B2

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Abstract

A display device includes a timing controller which transmits a vertical clock signal having rising edges and falling edges to a gate driver and a gate driver which receives the vertical clock signal, to generate a first gate clock signal and a first inverted gate clock signal in accordance with one of the rising edges and the falling edges of the vertical clock signal, and to generate a second gate clock signal and a second inverted gate clock signal in accordance with a remaining one of the rising edges and the falling edges of the vertical clock signal.

Claims (34)

1. A display device comprising:

a timing controller which transmits a vertical clock signal having rising edges and falling edges; and

a gate driver which receives the vertical clock signal, generates a first gate clock signal and a first inverted gate clock signal in accordance with one of the rising edges and the falling edges of the vertical clock signal, and generates a second gate clock signal and a second inverted gate clock signal in accordance with a remaining one of the rising edges and the falling edges of the vertical clock signal.

2. The display device of claim 1 , further comprising a display panel including a plurality of pixels,

wherein the gate driver is combined with the display panel in a form of an amorphous silicon gate.

3. The display device of claim 1 ,

wherein the first gate clock signal and the first inverted gate clock signal have opposite phases to each other, and

wherein the second gate clock signal and the second inverted gate clock signal have opposite phases to each other.

4. The display device of claim 1 , wherein the gate driver reduces a voltage level of the first gate clock signal to a lower level and increases a voltage level of the first inverted gate clock signal to a higher level at a first rising edge of the vertical clock signal and increases the voltage level of the first gate clock signal to a higher level and reduces the voltage level of the first inverted gate clock signal to a lower level at a second rising edge of the vertical clock signal.

5. The display device of claim 1 , wherein the gate driver reduces a voltage level of the second gate clock signal to a lower level and increases a voltage level of the second inverted gate clock signal to a higher level at a first falling edge of the vertical clock signal and increases the voltage level of the second gate clock signal to a higher level and reduces the voltage level of the second inverted gate clock signal to a lower level at a second falling edge of the vertical clock signal.

6. The display device of claim 1 , further comprising a data driver, wherein the data driver reduces a voltage level of the first gate clock signal or a voltage level of the second gate clock signal to an intermediate level at the first rising edge of the vertical clock signal, reduces the voltage level of the first gate clocks signal or the voltage level of the second gate clock signal to a low level after a predetermined first intermediate period, increases a voltage level of the first inverted gate clock signal or a voltage level of the second inverted gate clock signal to an intermediate level at the first rising edge, and increases the voltage level of the first inverted gate clock signal or the voltage level of the second inverted gate clock signal to a high level after the predetermined first intermediate period.

7. The display device of claim 6 , wherein the data driver increases the voltage level of the first gate clock signal or the voltage level of the second gate clock signal to an intermediate level at the second rising edge of the vertical clock signal, increases the voltage level of the first gate clocks signal or the voltage level of the second gate clock signal to a high level after a predetermined second intermediate period, reduces the voltage level of the first inverted gate clock signal or the voltage level of the second inverted gate clock signal to an intermediate level at the second rising edge, and reduces the voltage level of the first inverted gate clock signal or the voltage level of the second inverted gate clock signal to a low level after the predetermined second intermediate period.

8. The display device of claim 7 , wherein the gate driver includes an output end of the first gate clock signal and an output end of the first inverted gate clock signal shorted to perform charge share operation in one of the predetermined first intermediate period and the predetermined second intermediate period.

9. A method of driving a display device, the method comprising:

generating a vertical clock signal having rising edges and falling edges; and

generating a gate clock signals,

wherein the generating the gate clock signals comprises:

generating a first gate clock signal and a first inverted gate clock signal in accordance with one of the rising edges and the falling edges of the vertical clock signal; and

generating a second gate clock signal and a second inverted gate clock signal in accordance with a remaining one of the rising edges and the falling edges of the vertical clock signal.

10. The method of claim 9 , wherein the first gate clock signal and the first inverted gate clock signal have opposite phases to each other, and

wherein the second gate clock signal and the second inverted gate clock signal have opposite phases to each other.

11. The method of claim 9 , wherein the generating the gate clock signals further comprises:

reducing a voltage level of the first gate clock signal to a lower level and increasing a voltage level of the first inverted gate clock signal to a higher level at a first rising edge of the vertical clock signal; and

increasing the voltage level of the first gate clock signal to a higher level and reducing the voltage level of the first inverted gate clock signal to a lower level at a second rising edge of the vertical clock signal.

12. The method of claim 9 , wherein the generating the gate clock signals further comprises:

reducing a voltage level of the second gate clock signal to a lower level and increasing a voltage level of the second inverted gate clock signal to a higher level at a first falling edge of the vertical clock signal; and

increasing the voltage level of the second gate clock signal to a higher level and reducing the voltage level of the second inverted gate clock signal to a lower level at a second falling edge of the vertical clock signal.

13. The method of claim 9 , wherein the generating the gate clock signals further comprises:

reducing a voltage level of the first gate clock signal or a voltage level of the second gate clock signal to an intermediate level at the first rising edge of the vertical clock signal and reducing the voltage level of the first gate clock signal or the voltage level of the second gate clock signal to a low level after a predetermined first intermediate period; and

increasing a voltage level of the first inverted gate clock signal or a voltage level of the second inverted gate clock signal to an intermediate level at the first rising edge and increasing the voltage level of the first inverted gate clock signal or the voltage level of the second inverted gate clock signal to a high level after the predetermined first intermediate period.

14. The method of claim 13 , wherein the generating the gate clock signals further comprises:

increasing the voltage level of the first gate clock signal or the voltage level of the second gate clock signal to an intermediate level at the second rising edge of the vertical clock signal and increasing the voltage level of the first gate clocks signal or the voltage level of the second gate clock signal to a high level after a predetermined second intermediate period; and

reducing the voltage level of the first inverted gate clock signal or the voltage level of the second inverted gate clock signal to an intermediate level at the second rising edge and reducing the voltage level of the first inverted gate clock signal or the voltage level of the second inverted gate clock signal to a low level after the predetermined second intermediate period.

15. The method of claim 14 , wherein the generating the gate clock signals comprises having an output end of the first gate clock signal and an output end of the first inverted gate clock signal shorted to perform charge share operation in one of the predetermined first intermediate period and the predetermined second intermediate period.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2016

From: CHOI, GEUN HYUK; LEE, SANG HYUN; LEE, HYO CHUL; CHOI, JAE HO; HONG, HYUN SEOK

To: SAMSUNG DISPLAY CO., LTD.

Reel/Frame 040214/0767 →

Priority Claims (1)

KR 10-2015-0170708 · Dec 2, 2015 · national

Continuity (1)

Related Publication 20170162123A1 · Jun 8, 2017

Cited By (1)

US 12,283,215