IP Library Granted Patent US 10,050,432
Granted Patent B2
US 10,050,432 · App. 15/176,399 · Granted Aug 14, 2018

Apparatus with load dump protection

Inventor: Szu-chun Tsao (Yilan, TW)
Assignee: Elite Semiconductor Memory Technology Inc.
H02H3/22H02H1/0007H02H3/20H02H7/067H02H7/0838H02H9/04
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Quick Facts
Patent No.
US 10,050,432
App. No.
15/176,399
Granted
Aug 14, 2018
Kind
B2
Abstract

An apparatus with load dump protection incorporates first and second half-bridge circuits, first and second comparators, and first and second clamping circuits. The first comparator compares a supply voltage with a first set voltage and generates a first comparison signal while the supply voltage exceeds the first set voltage. The second comparator compares the supply voltage with a second set voltage and generates a second comparison signal while the supply voltage exceeds the second set voltage. The first clamping circuit divides the supply voltage and provides a divided voltage to the first half-bridge circuit in response to the second comparison signal. The second clamping circuit divides the supply voltage and provides a divided voltage to the second half-bridge circuit in response to the second comparison signal.

Claims (17)

1. An apparatus for driving a load between first and second output nodes, comprising:

a first half-bridge circuit comprising first and second transistors connected in series between a supply voltage and a reference voltage, with the first output node between the first and second transistors;

a second half-bridge circuit comprising third and fourth transistors connected in series between the supply voltage and the reference voltage, with the second output node between the third and fourth transistors;

a first comparator configured to compare the supply voltage with a first set voltage and generate a first comparison signal while the supply voltage exceeds the first set voltage;

a second comparator configured to compare the supply voltage with a second set voltage and generate a second comparison signal while the supply voltage exceeds the second set voltage;

a first clamping circuit configured to divide the supply voltage and provide a first divided voltage at the first output node in response to the second comparison signal; and

a second clamping circuit configured to divide the supply voltage and provide a second divided voltage at the second output node in response to the second comparison signal;

wherein the second set voltage is larger than the first set voltage; and

wherein the first, second, third, and fourth transistors are turned off in response to the first comparison signal.

2. The apparatus of claim 1 , wherein the first transistor is a P-channel MOSFET, the second transistor is a N-channel MOSFET, the third transistor is a P-channel MOSFET, and the fourth transistor is a N-channel MOSFET.

3. The apparatus of claim 1 , wherein the first transistor is a N-channel MOSFET, the second transistor is a N-channel MOSFET, the third transistor is a N-channel MOSFET, and the fourth transistor is a N-channel MOSFET.

4. The apparatus of claim 1 , wherein the first clamping circuit comprises a plurality of resistors serially connected to the supply voltage through a fifth transistor, the fifth transistor is turned on in response to the second comparison signal.

5. The apparatus of claim 1 , wherein the second clamping circuit comprises a plurality of resistors serially connected to the supply voltage through a sixth transistor, the sixth transistor is turned on in response to the second comparison signal.

6. The apparatus of claim 1 , wherein the first clamping circuit comprises a plurality of capacitors serially connected to the supply voltage through a seventh transistor, the seventh transistor is turned on in response to the second comparison signal.

7. The apparatus of claim 1 , wherein the second clamping circuit comprises a plurality of capacitors serially connected to the supply voltage through an eighth transistor, the eighth transistor is turned on in response to the second comparison signal.

8. The apparatus of claim 1 , wherein the first clamping circuit provides the first divided voltage by dividing the supply voltage at a ratio of 2.

9. The apparatus of claim 1 , wherein the second clamping circuit provides the second divided voltage by dividing the supply voltage at a ratio of 2.

Assignments (2)
CHANGE OF NAME Recorded Jun 25, 2025
From: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
To: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
Reel/Frame 071703/0241 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2016
From: TSAO, SZU-CHUN
To: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
Reel/Frame 038842/0304 →
Continuity (1)
Related Publication 20170358918A1 · Dec 14, 2017