Instruction and logic for scheduling instructions

1. A processor, comprising:

a front end including circuitry to:

determine that an acyclical thread assignment scheme is to be applied to a first block of code received at the processor;

determine that a cyclical thread assignment scheme is to be applied to a second block of code received at the processor;

based upon applying the acyclical thread assignment scheme, assign the first block of code to a static logical thread; and

based upon applying the cyclical thread assignment scheme, assign the second block of code to a rotating logical thread; and

a scheduler including circuitry to:

assign the static logical thread to a first physical thread;

assign the static logical thread to the first physical thread upon each subsequent control flow instruction of the static logical thread;

assign the rotating logical thread using a loop of cycle thread assignment iterations, wherein the loop of cyclical thread assignment iterations comprises:

assigning the rotating logical thread to a second physical thread; and

assigning the rotating logical thread to a third physical thread upon a subsequent execution of the rotating logical thread.

2. The processor of claim 1 , wherein the front end further includes, as part of the acyclical thread assignment scheme, circuitry to:

move atoms from within a second block of code to an earlier, first block of code; and

assign atoms remaining in the second block of code to the rotating logical thread.

3. The processor of claim 1 , wherein the front end further includes, as part of the acyclical thread assignment scheme, circuitry to:

move atoms from within a second block of code to an earlier, first block of code;

prioritize the moved atoms by assigning the moved atoms to the rotating logical thread; and

assign branch instructions to the static logical thread.

4. The processor of claim 3 , wherein the front end further includes, as part of the acyclical thread assignment scheme, circuitry to assign remaining instructions to another static logical thread.

5. The processor of claim 1 , wherein the front end further includes circuitry to, as part of the cyclical thread assignment scheme:

determine any recurrence chains and loop carried dependence (LCD) chains in a loop;

for each recurrence chain and LCD chain, schedule atoms in the chain to execute closer to other atoms of the chain in a first iteration of the loop; and

schedule other atoms of the loop to overlap with a beginning of a second iteration of the loop.

6. The processor of claim 1 , wherein the front end further includes circuitry to, as part of the cyclical thread assignment scheme:

determine a recurrence chain in a loop;

schedule all atoms of the recurrence chain in the fixed logical thread; and

schedule remaining atoms in the rotating logical thread.

7. The processor of claim 1 , wherein the front end further includes circuitry to, as part of the cyclical thread assignment scheme:

determine a recurrence chain and a plurality of loop carried dependence (LCD) chains in a loop;

schedule all atoms of the recurrence chain in the fixed logical thread; and

schedule each LCD chain in a respective LCD rotating logical thread; and

schedule remaining atoms in the rotating logical thread.

8. A method comprising, within a processor:

determining to apply an acyclical thread assignment scheme to a first block of code received at the processor;

determining to apply a cyclical thread assignment scheme to a second block of code received at the processor;

based upon applying the acyclical thread assignment scheme, assigning the first block of code to a static logical thread; and

based upon applying the cyclical thread assignment scheme, assigning the second block of code to a rotating logical thread;

assigning the static logical thread to a first physical thread;

assigning the static logical thread to the first physical thread upon each subsequent control flow execution of the static logical thread;

assigning the rotating logical thread using a loop of cyclical thread assignment iterations, wherein the loop of cyclical thread assignment iterations comprises:

assigning the rotating logical thread to a second physical thread; and

assigning the rotating logical thread to a third physical thread upon a subsequent execution of the rotating logical thread.

9. The method of claim 8 , further comprising, as part of the acyclical thread assignment scheme, assigning remaining instructions to another static logical thread.

10. A system comprising: a processor comprising:

a front end, including circuitry to:

determine whether to apply an acyclical thread assignment scheme to a first block of code received at the processor;

determine whether to apply a cyclical thread assignment scheme to a second block of code received at the processor;

based upon applying the acyclical thread assignment scheme, assign the first block of code to a static logical thread; and

based upon applying the cyclical thread assignment scheme to be cyclical, assign the second block of code to a rotating logical thread; and

a scheduler, including circuitry to:

assign the static logical thread to a first physical thread;

assign the static logical thread to the first physical thread upon each subsequent control flow execution of the static logical thread;

assign the rotating logical thread using a loop of cycle thread assignment iterations, wherein the loop of cyclical thread assignment iterations comprises:

assigning the rotating logical thread to a second physical thread; and

assigning the rotating logical thread to a third physical thread upon a subsequent execution of the rotating logical thread.

11. The system of claim 10 , wherein the front end further includes circuitry to, as part of the acyclical thread assignment scheme:

move atoms from within a second block of code to an earlier, first block of code; and

assign atoms remaining in the second block of code to the rotating logical thread.

12. The system of claim 10 , wherein the front end further includes circuitry to, as part of the acyclical thread assignment scheme:

move atoms from within a second block of code to an earlier, first block of code;

prioritize the moved atoms by assigning the moved atoms to the rotating logical thread; and

assign branch instructions to the static logical thread.

13. The system of claim 12 , wherein the front end further includes circuitry to, as part of the acyclical thread assignment scheme, a twelfth logic to assign remaining instructions to another static logical thread.

14. The system of claim 10 , wherein the front end further includes circuitry to, as part of the cyclical thread assignment scheme:

determine any recurrence chains and loop carried dependence (LCD) chains in a loop;

for each recurrence chain and LCD chain, schedule atoms in the chain to execute closer to other atoms of the chain in a first iteration of the loop; and

schedule other atoms of the loop to overlap with a beginning of a second iteration of the loop.

15. The system of claim 10 , wherein the front end further includes circuitry to, as part of the cyclical thread assignment scheme:

determine a recurrence chain in a loop;

schedule all atoms of the recurrence chain in the fixed logical thread; and

schedule remaining atoms in the rotating logical thread.

16. The system of claim 10 , wherein the front end further includes circuitry to, as part of the cyclical thread assignment scheme:

determine a recurrence chain and a plurality of loop carried dependence (LCD) chains in a loop;

schedule all atoms of the recurrence chain in the fixed logical thread; and

schedule each LCD chain in a respective LCD rotating logical thread; and

schedule remaining atoms in the rotating logical thread.