Data control circuit and flat panel display device including the same
A data control circuit includes a MUX driver that electrically connects a first channel of a data driver and one of the pixels in a first pixel group of a display panel in response to a first control signal, and electrically connects a second channel of the data driver and one of the pixels in a second pixel group of the display panel in response to a second control signal; and a MUX controller that outputs the first and second control signals.
1. A data control circuit, comprising:
a MUX driver that electrically connects a first channel of a data driver and one of the pixels in a first pixel group of a display panel in response to a first control signal, and electrically connects a second channel of the data driver and one of the pixels in a second pixel group of the display panel in response to a second control signal; and
a MUX controller that outputs the first and second control signals,
wherein the first control signal includes a first plurality of MUX signals each corresponding to respective pixels of the first pixel group,
wherein the second control signal includes a second plurality of MUX signals each corresponding to respective pixels of the second pixel group, and
wherein the first and second control signals are set to a voltage level between +8 V and −3.0 V if a data voltage has a positive polarity and a voltage level between +3.0 V and −8 V if the data voltage has a negative polarity.
2. The data control circuit of claim 1 , wherein the MUX driver comprises:
first, third, and fifth switching transistors including each of gate terminals to which the first control signal is applied, each of drain terminals connected to the first channel, and each of source terminals connected to the pixels in the first pixel group; and
second, fourth, and sixth switching transistors including each of gate terminals to which the second control signal is applied, each of drain terminals connected to the second channel, and each of source terminals connected to the pixels in the second pixel group.
3. The data control circuit of claim 1 , wherein the first and second control signals have the same voltage swing.
4. The data control circuit of claim 1 , wherein the first and second control signals have opposite polarities.
5. The data control circuit of claim 1 , wherein the first and second control signals are three-phase signals, whose high levels sequentially alternate for each ⅓ horizontal period.
6. The data control circuit of claim 1 , wherein the first and second pixel groups are connected to a gate driver that supplies a gate high voltage and a gate low voltage, and the maximum voltage level and minimum voltage level of the first and second control signals correspond to the gate high voltage and gate low voltage.
7. A flat panel display device, comprising:
a display panel including a first pixel group that operates with a first polarity and a second pixel group that operates with a second polarity;
a data driver including first and second channels that supply the first and second pixel groups with a data voltage for a video;
a data drive circuit including a MUX driver and a MUX controller for outputting first and second control signals, the MUX driver electrically connecting the first channel and one of the pixels in the first pixel group in response to the first control signal, and electrically connecting the second channel and one of the pixels in the second pixel group in response to the second control signal,
wherein the first control signal includes a first plurality of MUX signals each corresponding to respective pixels of the first pixel group,
wherein the second control signal includes a second plurality of MUX signals each corresponding to respective pixels of the second pixel group, and
wherein the first and second control signals are set to a voltage level between +8 V and −3.0 V if a data voltage has a positive polarity and a voltage level between +3.0 V and −8 V if the data voltage has a negative polarity.
8. The flat panel display device of claim 7 , wherein the first pixel group includes first, third, and fifth pixels and the second pixel group includes second, fourth, and sixth pixels,
wherein the first plurality of MUX signals of the first control signal includes first to third MUX signals respectively corresponding to the first pixel group, and
wherein the first plurality of MUX signals of the second control signal includes fourth to sixth MUX signals respectively corresponding to the second pixel group.
9. The data control circuit of claim 1 , wherein the first pixel group includes first, third, and fifth pixels and the second pixel group includes second, fourth, and sixth pixels,
wherein the first plurality of MUX signals of the first control signal includes first to third MUX signals respectively corresponding to the first pixel group, and
wherein the first plurality of MUX signals of the second control signal includes fourth to sixth MUX signals respectively corresponding to the second pixel group.
10. A data control circuit, comprising:
a MUX driver that electrically connects a first channel of a data driver and one of the pixels in a first pixel group of a display panel in response to a first control signal, and electrically connects a second channel of the data driver and one of the pixels in a second pixel group of the display panel in response to a second control signal; and
a MUX controller that outputs the first and second control signals,
wherein the first and second control signals are set to a voltage level between +8 V and −3.0 V if a data voltage has a positive polarity and a voltage level between +3.0 V and −8 V if the data voltage has a negative polarity.