IP Library › Granted Patent US 10,056,347
Granted Patent B2
US 10,056,347 · App. 15/413,058 · Granted Aug 21, 2018

Bump structure for yield improvement

Inventors: Tzu-Wei Chiu (Hsin-Chu, TW); Tzu-Yu Wang (Taipei, TW); Shang-Yun Hou (Jubei, TW); Shin-Puu Jeng (Hsin-Chu, TW); Hsien-Wei Chen (Hsin-Chu, TW); Hung-An Teng (Taoyuan, TW); Wei-Cheng Wu (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company
H01L24/81B23K1/0016C23C14/165C23C14/34C23C18/32C23C18/42H01L24/11H01L24/13H01L24/16H01L25/0657H01L25/50H01L2224/114H01L2224/119H01L2224/1145H01L2224/1146H01L2224/1147H01L2224/11903H01L2224/13019H01L2224/13082H01L2224/13147H01L2224/13166H01L2224/13564H01L2224/13644H01L2224/13655H01L2224/13664H01L2224/16148H01L2224/8112H01L2224/81193H01L2224/81345H01L2224/81365H01L2224/81815H01L2225/06513H01L2225/06593H01L2924/014
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Quick Facts
Patent No.
US 10,056,347
App. No.
15/413,058
Filed
Jan 23, 2017
Granted
Aug 21, 2018
Kind
B2
Art Unit
2892
USPC
257/737
Abstract

A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

Claims (56)

1. A method of forming a semiconductor device, the method comprising:

forming a first non-flat portion on a first bump, the first non-flat portion having a plurality of discrete recesses;

covering the first bump with a first material;

forming a second non-flat portion on a second bump, the second non-flat portion having a plurality of projections, the first non-flat portion having a same number of recesses as the second non-flat portion has projections;

covering the second non-flat portion with a second material;

laterally aligning the recesses of the first non-flat portion with the projections of the second non-flat portion; and

reflowing the first material and the second material, thereby forming a bond between the first non-flat portion and the second non-flat portion.

2. The method of claim 1 , wherein the second material is solder and the first material is electroless nickel electroless palladium immersion gold.

3. The method of claim 1 , wherein the second non-flat portion comprises a flat shoulder along a periphery.

4. The method of claim 1 , wherein forming the second non-flat portion on the second bump comprises:

forming a first patterned mask over a first passivation layer, the first passivation layer having a first opening, the first opening exposing a first contact pad, the first patterned mask having a second opening, the first contact pad being laterally over in the second opening;

forming a first conductive element in the second opening, the first conductive element extending above an upper surface of the first passivation layer;

removing the first patterned mask;

forming a second patterned mask over the first passivation layer, the second patterned mask having a third opening, a width of the third opening being greater than a width of the first conductive element; and

forming a second conductive element over the first conductive element in the third opening, the first conductive element and the second conductive element forming the second non-flat portion on the second bump.

5. The method of claim 4 , wherein forming the first non-flat portion on the first bump comprises:

forming a third patterned mask over a second passivation layer, the second passivation layer having a fourth opening, the fourth opening exposing a second contact pad, the third patterned mask having a fifth opening, the fifth opening being laterally over the second contact pad and an upper surface of the second passivation layer; and

forming a second conductive element in the fifth opening, the second conductive element extending above an upper surface of the second passivation layer, an upper surface of the second conductive element having a second recess within the fourth opening, the second conductive element forming the first non-flat portion on the first bump.

6. The method of claim 1 , wherein after reflowing a first projection of the projections extends into a first recess of the recesses.

7. A method of forming a device, the method comprising:

forming a passivation layer over a substrate, the substrate having a contact pad, the passivation layer having a first opening, the first opening exposing the contact pad;

forming a first patterned mask over the passivation layer, the first patterned mask having a second opening, the contact pad being laterally below the second opening;

forming a first conductive element in the second opening, the first conductive element extending above an upper surface of the passivation layer;

removing the first patterned mask;

forming a second patterned mask over the passivation layer, the second patterned mask having a third opening, a width of the third opening being greater than a width of the first conductive element;

forming a second conductive element over the first conductive element in the third opening, the first conductive element and the second conductive element forming a first bump having a first projection;

after forming the second conductive element, removing the second patterned mask; and

attaching the first bump to a second bump, the second bump having a first recess, wherein after the attaching the first projection is aligned with the first recess.

8. The method of claim 7 , further comprising forming an insulating layer along sidewalls of the first opening.

9. The method of claim 8 , wherein the insulating layer extends along an upper surface of the passivation layer.

10. The method of claim 8 , wherein the second conductive element extends over an upper surface of the insulating layer.

11. The method of claim 8 , wherein a width of the third opening is less than a width of the insulating layer.

12. The method of claim 7 , further comprising, prior to forming the first patterned mask, sputtering a conductive layer over the passivation layer, the first patterned mask being on the conductive layer.

13. The method of claim 12 , wherein the conductive layer comprises a Ti layer and a Cu layer.

14. A method of forming a device, the method comprising:

forming a first passivation layer over a first substrate, the first substrate having a first contact pad, the first passivation layer having a first opening, the first opening exposing the first contact pad;

forming a first patterned mask over the first passivation layer, the first patterned mask having a second opening over the contact pad and an upper surface of the first passivation layer being exposed in the second opening;

forming a first conductive element in the second opening, the first conductive element extending above an upper surface of the first passivation layer, an upper surface of the first conductive element having a first recess within the first opening, the first conductive element forming a first bump;

removing the first patterned mask;

forming a second conductive element over the first conductive element, the second conductive element having a lower reflow temperature than the first conductive element;

forming a first projection of a second bump on a second substrate, comprising:

forming a second patterned mask over a second passivation layer, the second passivation layer having a second opening, the second opening exposing a second contact pad, the second patterned mask having a third opening, the second contact pad being under in the third opening;

forming a third conductive element in the third opening, the third conductive element extending above an upper surface of the second passivation layer;

removing the second patterned mask;

forming a third patterned mask over the second passivation layer, the third patterned mask having a fourth opening, a width of the fourth opening being greater than a width of the third conductive element;

forming a fourth conductive element over the third conductive element in the fourth opening, the fourth conductive element and the third conductive element forming the second bump; and

forming a fifth conductive element over the fourth conductive element;

aligning the first projection of the second bump on the second substrate to the first recess of the first bump; and

reflowing the second conductive element and the fifth conductive element.

15. The method of claim 14 , wherein forming the first passivation layer comprises forming a second passivation layer and a third passivation layer over the second passivation layer.

16. The method of claim 15 , wherein sidewalls of the second passivation layer are continuous with sidewalls of the third passivation layer.

17. The method of claim 14 , further comprising, prior to forming the first patterned mask, sputtering a conductive layer on the first passivation layer, the first patterned mask being formed on the conductive layer.

18. The method of claim 17 , further comprising, after removing the first patterned mask, removing exposed portions of the conductive layer.

19. The method of claim 18 , wherein the second conductive element extends along sidewalls of the first conductive element.

20. The method of claim 14 , wherein the second conductive element is interposed between sidewalls of the first opening.

21. The method of claim 14 , wherein the first projection is one of a plurality of projections of the second bump.

Continuity (2)
Division 13558082 · Jul 25, 2012
Related Publication 20170133346A1 · May 11, 2017
Cited By (2)
US 12,354,980 US 12,713,990