Gate stack integrated metal resistors
Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.
1. A method of forming a semiconductor device; comprising:
forming an active gate stack on a substrate, the active gate stack comprising a self-aligning cap and a first gate metal;
forming epitaxial contacts in the active gate stack;
forming a dummy gate stack on an oxide layer disposed on the substrate, the dummy gate stack comprising a self-aligned contact cap and a second gate metal;
depositing a resist mask onto the semiconductor device;
patterning the resist mask such that the dummy gate stack is exposed;
removing the self-aligning cap and the second gate metal from the exposed gate stack to form an exposed dummy gate stack trench;
depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed dummy gate stack trench.
2. The method of claim 1 , wherein the method further comprises forming a bar contact and contact via above the metal resistor and depositing a dielectric layer above the bar contact.
3. The method of claim 1 , wherein the resist mask is polymethyl methacrylate.
4. The method of claim 1 , wherein patterning the resist mask comprises using electron beam lithography.
5. The method of claim 1 , further comprising depositing an oxide layer above the metal resistor.
6. The method of claim 1 , wherein the epitaxial contacts comprise a source region and a drain region.
7. The method of claim 1 , further comprising forming a low-k dielectric layer in the active gate stack.
8. The method of claim 1 , further comprising forming a SiN liner in the active gate stack.
9. The method of claim 1 , wherein the epitaxial contacts comprise a material selected from the group consisting of silicon or silicon-germanium containing p-type dopants, silicon or silicon-germanium containing n-type dopants, and combinations thereof.
10. The method of claim 1 , further comprising forming a low-k dielectric oxide over the epitaxial contacts.