IP Library Granted Patent US 10,057,531
Granted Patent B2
US 10,057,531 · App. 15/893,425 · Granted Aug 21, 2018

Solid-state image pickup device and method for driving the same in solid-state imaging pickup device and method for driving the same in a number of modes

Inventors: Yoshikazu Nitta (Tokyo, JP); Noriyuki Fukushima (Kanagawa, JP); Yoshinori Muramatsu (Kanagawa, JP); Yukihiko Yasui (Kanagawa, JP)
Assignee: Sony Corporation
H04N5/378H03M1/1023H04N3/1562H04N5/2253H04N5/347H04N5/3742H04N5/37455H03M1/56
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Quick Facts
Patent No.
US 10,057,531
App. No.
15/893,425
Granted
Aug 21, 2018
Kind
B2
Abstract

A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.

Claims (47)

1. An imaging device comprising:

a pixel array including a plurality of pixels which are two-dimensionally arranged in columns and rows, the plurality of pixels including a first pixel, a second pixel, a third pixel, and a fourth pixel;

a plurality of signal lines including a first signal line coupled to the first pixel, a second signal line coupled to the second pixel, a third signal line coupled to the third pixel, and a fourth signal line coupled to the fourth pixel;

a first comparator of a first Analog-to-Digital (A/D) converter coupled to the first signal line;

a plurality of switch circuits including a first switch circuit and a second switch circuit;

a second comparator of a second A/D converter selectively coupled to the second signal line and the third signal line through the first switch circuit;

a third comparator of a third A/D converter selectively coupled to the second signal line or the third signal line through the second switch circuit; and

a fourth comparator of a fourth A/D converter coupled to the fourth signal line,

wherein the first switch circuit couples the second signal line to the second comparator at a same time the second switch circuit couples the third signal line to the third comparator.

2. The imaging device according to claim 1 , further comprising a reference signal generation circuit that supplies a reference signal to the first comparator.

3. The imaging device according to claim 1 , wherein the first A/D converter includes a first counter and a first memory.

4. The imaging device according to claim 1 , wherein the first comparator receives a first output from the first signal line at a same time the second comparator receives a second output from the second signal line via the first switch circuit.

5. The imaging device according to claim 1 , wherein the first switch circuit couples the third signal line to the second comparator at a same time the second switch circuit couples the second signal line to the third comparator.

6. The imaging device according to claim 5 , wherein the first switch circuit is adjacent to the second switch circuit.

7. The imaging device according to claim 5 , wherein the first A/D converter is adjacent to the second A/D converter.

8. The imaging device according to claim 1 , wherein each pixel of the plurality of the pixels includes a photoelectric conversion element, a reset transistor, a transfer transistor, an amplifier transistor, and a select transistor.

9. The imaging device according to claim 1 , wherein the first signal line is not coupled to the second signal line.

10. The imaging device according to claim 1 , wherein the third signal line is not coupled to the fourth signal line.

11. The imaging device according to claim 1 , wherein the second signal line is between the first signal line and the third signal line.

12. The imaging device according to claim 1 , wherein the fourth signal line is between the third signal line and a fifth signal line.

13. The imaging device according to claim 1 , wherein the second comparator is directly coupled to the first switch circuit.

14. The imaging device according to claim 3 , wherein the second comparator is directly coupled to the second switch circuit.

15. An electronic apparatus comprising:

an optical system; and

an imaging device including:

a pixel array including a plurality of pixels which are two-dimensionally arranged in columns and rows, the plurality of pixels including a first pixel, a second pixel, a third pixel, and a fourth pixel,

a plurality of signal lines including a first signal line coupled to the first pixel, a second signal line coupled to the second pixel, a third signal line coupled to the third pixel, and a fourth signal line coupled to the fourth pixel,

a first comparator of a first Analog-to-Digital (A/D) converter coupled to the first signal line,

a plurality of switch circuits including a first switch circuit and a second switch circuit,

a second comparator of a second A/D converter selectively coupled to the second signal line and the third signal line through the first switch circuit,

a third comparator of a third A/D converter selectively coupled to the second signal line or the third signal line through the second switch circuit,

a fourth comparator of a fourth A/D converter coupled to the fourth signal line,

wherein the first switch circuit couples the second signal line to the second comparator at a same time the second switch circuit couples the third signal line to the third comparator, and

a plurality of color filters arranged above the plurality of pixels.

16. The electronic apparatus according to claim 15 , further comprising a reference signal generation circuit that supplies a reference signal to the first comparator.

17. The electronic apparatus according to claim 15 , wherein the first A/D converter includes a first counter and a first memory.

18. The electronic apparatus according to claim 15 , wherein the first comparator receives a first output from the first signal line at a same time the second comparator receives a second output from the second signal line via the first switch circuit.

19. The electronic apparatus according to claim 15 , wherein the first switch circuit couples the third signal line to the second comparator at a same time the second switch circuit couples the second signal line to the third comparator.

20. The electronic apparatus according to claim 19 , wherein the first switch circuit is adjacent to the second switch circuit.

21. The electronic apparatus according to claim 19 , wherein the first A/D converter is adjacent to the second A/D converter.

22. The electronic apparatus according to claim 19 , wherein each pixel of the plurality of the pixels includes a photoelectric conversion element, a reset transistor, a transfer transistor, an amplifier transistor, and a select transistor.

23. The electronic apparatus according to claim 15 , wherein the first signal line is not coupled to the second signal line.

24. The electronic apparatus according to claim 15 , wherein the third signal line is not coupled to the fourth signal line.

25. The electronic apparatus according to claim 15 , wherein the second signal line is between the first signal line and the third signal line.

26. The electronic apparatus according to claim 15 , wherein the fourth signal line is between the third signal line and a fifth signal line.

27. The electronic apparatus according to claim 15 , wherein the second comparator is directly coupled to the first switch circuit.

28. The electronic apparatus according to claim 26 , wherein the second comparator is directly coupled to the second switch circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2020
From: NITTA, YOSHIKAZU; FUKUSHIMA, NORIYUKI; MURAMATSU, YOSHINORI; YASUI, YUKIHIKO
To: SONY CORPORATION
Reel/Frame 052710/0496 →
Priority Claims (2)
JP 2004-045943 · Feb 23, 2004 · national
JP 2004-208038 · Jul 15, 2004 · national
Continuity (10)
Continuation 15644539 · Jul 7, 2017
Continuation 15180300 · Jun 13, 2016
Continuation 14957407 · Dec 2, 2015
Continuation 14294942 · Jun 3, 2014
Continuation 14023239 · Sep 10, 2013
Continuation 13094420 · Apr 26, 2011
Continuation 12772573 · May 3, 2010
Continuation 12419077 · Apr 6, 2009
Division 11058851 · Feb 16, 2005
Related Publication 20180184032A1 · Jun 28, 2018