Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having a gate back-bias rail(s), and related systems and methods
Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having gate back-bias rail(s) are disclosed. Related systems and methods are also disclosed. In one aspect, a SOI CMOS standard library cell circuit is provided that is comprised of one or more standard library cells. Each standard library cell includes one or more PMOS channel regions and one or more NMOS channel regions. Each standard library cell has one or more gate back-bias rails disposed adjacent to PMOS and NMOS channel regions. The gate back-bias rails are configured to apply bias voltages to corresponding PMOS and NMOS channel regions to adjust threshold voltages of PMOS and NMOS transistors associated with the PMOS and NMOS channel regions, respectively. Voltage biasing can be controlled to adjust timing of an IC using SOI CMOS standard library cell circuits to achieve design timing targets without including timing closure elements that consume additional area.
1. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) cell circuit, comprising one or more standard library cells, each of the one or more standard library cells comprising:
one or more p-type metal oxide semiconductor (PMOS) channel regions having a PMOS channel width;
one or more PMOS transistors, each of the one or more PMOS transistors comprising a PMOS gate, a PMOS source, and a PMOS drain, where a distance between the PMOS source and the PMOS drain defines the PMOS channel width, each of the one or more PMOS transistors associated with one of the one or more PMOS channel regions;
one or more PMOS supply rails each configured to provide a supply voltage to a PMOS channel region among the one or more PMOS channel regions;
one or more n-type metal oxide semiconductor (NMOS) channel regions having an NMOS channel width;
one or more NMOS transistors, each of the one or more NMOS transistors comprising an NMOS gate, an NMOS source, and an NMOS drain, where a distance between the NMOS source and the NMOS drain defines the NMOS channel width, each of the one or more NMOS transistors associated with one of the one or more NMOS channel regions;
one or more NMOS supply rails each configured to provide the supply voltage to an NMOS channel region among the one or more NMOS channel regions;
one or more PMOS gate back-bias rails each disposed in a corresponding PMOS channel region among the one or more PMOS channel regions, wherein each of the one or more PMOS gate back-bias rails has a width less than the PMOS channel width,
each of the one or more PMOS gate back-bias rails configured to apply a PMOS bias voltage only to the corresponding PMOS channel region to adjust a threshold voltage of the one or more PMOS transistors associated with the corresponding PMOS channel region; and
one or more NMOS gate back-bias rails each disposed in a corresponding NMOS channel region among the one or more NMOS channel regions, wherein each of the one or more NMOS gate back-bias rails has a width less than the NMOS channel width,
each of the one or more NMOS gate back-bias rails configured to apply an NMOS bias voltage only to the corresponding NMOS channel region to adjust a threshold voltage of the one or more NMOS transistors associated with the corresponding NMOS channel region.
2. The SOI CMOS cell circuit of claim 1 , wherein:
each of the one or more PMOS gate back-bias rails is configured to apply a corresponding PMOS bias voltage to the corresponding PMOS channel region to adjust a threshold voltage of a PMOS transistor associated with the corresponding PMOS channel region; and
each of the one or more NMOS gate back-bias rails is configured to apply a corresponding NMOS bias voltage to the corresponding NMOS channel region to adjust a threshold voltage of an NMOS transistor associated with the corresponding NMOS channel region.
3. The SOI CMOS cell circuit of claim 1 , wherein:
each of the one or more PMOS gate back-bias rails is comprised of metal; and
each of the one or more NMOS gate back-bias rails is comprised of metal.
4. The SOI CMOS cell circuit of claim 1 , wherein:
each of the one or more PMOS gate back-bias rails is comprised of polysilicon; and
each of the one or more NMOS gate back-bias rails is comprised of polysilicon.
5. The SOI CMOS cell circuit of claim 1 , wherein:
the one or more PMOS gate back-bias rails comprise a first PMOS gate back-bias rail and
a second PMOS gate back-bias rail, wherein:
the first PMOS gate back-bias rail is configured to apply a first PMOS bias voltage to the corresponding PMOS channel region to adjust the threshold voltage of the one or more PMOS transistors associated with the corresponding PMOS channel region; and
the second PMOS gate back-bias rail is configured to apply a second PMOS bias voltage to the corresponding PMOS channel region different from the PMOS channel region corresponding to the first PMOS gate back-bias rail to adjust the threshold voltage of the one or more PMOS transistors associated with the corresponding PMOS channel region; and
the one or more NMOS gate back-bias rails comprise a first NMOS gate back-bias rail and a second NMOS gate back-bias rail, wherein:
the first NMOS gate back-bias rail is configured to apply a first NMOS bias voltage to the corresponding NMOS channel region to adjust the threshold voltage of the one or more NMOS transistors associated with the corresponding NMOS channel region; and
the second NMOS gate back-bias rail is configured to apply a second NMOS bias voltage to the corresponding NMOS channel region different from the NMOS channel region corresponding to the first NMOS gate back-bias rail to adjust the threshold voltage of the one or more NMOS transistors associated with the corresponding NMOS channel region.
6. The SOI CMOS cell circuit of claim 1 integrated into an integrated circuit (IC).
7. The SOI CMOS cell circuit of claim 1 integrated into a device selected from the group consisting of a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player.
8. An integrated circuit (IC) chip, comprising:
a plurality of ICs, wherein each IC of the plurality of ICs comprises:
a plurality of silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits, comprising one or more standard library cells, each of the one or more standard library cells comprising:
one or more p-type metal oxide semiconductor (PMOS) channel regions having a PMOS channel width;
one or more PMOS transistors, each of the one or more PMOS transistors comprising a PMOS gate, a PMOS source, and a PMOS drain, where a distance between the PMOS source and the PMOS drain defines the PMOS channel width, each of the one or more PMOS transistors associated with one of the one or more PMOS channel regions;
one or more PMOS supply rails each configured to provide a supply voltage to a PMOS channel region among the one or more PMOS channel regions;
one or more n-type metal oxide semiconductor (NMOS) channel regions having an NMOS channel width;
one or more NMOS transistors, each of the one or more NMOS transistors comprising an NMOS gate, an NMOS source, and an NMOS drain, where a distance between the NMOS source and the NMOS drain defines the NMOS channel width, each of the one or more NMOS transistors associated with one of the one or more NMOS channel regions;
one or more NMOS supply rails each configured to provide the supply voltage to an NMOS channel region among the one or more NMOS channel regions;
one or more PMOS gate back-bias rails each disposed in a corresponding PMOS channel region among the one or more PMOS channel regions, wherein each of the one or more PMOS gate back-bias rails has a width less than the PMOS channel width,
each of the one or more PMOS gate back-bias rails configured to apply a PMOS bias voltage only to the corresponding PMOS channel region to adjust a threshold voltage of the one or more PMOS transistors associated with the corresponding PMOS channel region; and
one or more NMOS gate back-bias rails each disposed in a corresponding NMOS channel region among the one or more NMOS channel regions, wherein each of the one or more NMOS pate back-bias rails has a width less than the NMOS channel width,
each of the one or more NMOS gate back-bias rails configured to apply an NMOS bias voltage only to the corresponding NMOS channel region to adjust a threshold voltage of the one or more NMOS transistors associated with the corresponding NMOS channel region.
9. The IC chip of claim 8 , wherein
the one or more PMOS gate back-bias rails comprise a first PMOS gate back-bias rail and a second PMOS gate back-bias rail, wherein:
the first PMOS gate back-bias rail is configured to apply a first PMOS bias voltage to the corresponding PMOS channel region to adjust the threshold voltage of the one or more PMOS transistors associated with the corresponding PMOS channel region; and
the second PMOS gate back-bias rail is configured to apply a second PMOS bias voltage to the corresponding PMOS channel region different from the PMOS channel region corresponding to the first PMOS gate back-bias rail to adjust the threshold voltage of the one or more PMOS transistors associated with the corresponding PMOS channel region; and
the one or more NMOS gate back-bias rails comprise a first NMOS gate back-bias rail and a second NMOS gate back-bias rail, wherein:
the first NMOS gate back-bias rail is configured to apply a first NMOS bias voltage to the corresponding NMOS channel region to adjust the threshold voltage of the one or more NMOS transistors associated with the corresponding NMOS channel region; and
the second NMOS gate back-bias rail is configured to apply a second NMOS bias voltage to the corresponding NMOS channel region different from the NMOS channel region corresponding to the first NMOS gate back-bias rail to adjust the threshold voltage of the one or more NMOS transistors associated with the corresponding NMOS channel region.