Semiconductor device with epitaxial source/drain

1. A method for manufacturing a semiconductor device, comprising:

forming a fin extending in a first direction over a substrate;

forming a plurality of gate structures extending in a second direction overlying the fin, wherein the gate structures comprise:

a gate dielectric layer overlying the fin;

gate electrodes overlying the gate dielectric layer; and

insulating gate sidewalls on opposing lateral surfaces of the gate electrodes extending along the second direction;

removing a portion of the fin in a first region between adjacent gate structures to form a recess in the fin;

forming a conformally doped region in a surface of the recess;

removing the conformally doped region to form an enlarged recess; and

forming a source/drain region in a surface of the enlarged recess, wherein the source/drain region extends under insulating gate sidewalls of adjacent gate structures along the second direction.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the conformally doped region is formed by implanting a dopant into the surface of the recess.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the conformally doped region is formed by plasma doping.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein the conformally doped region has a thickness of about 0.5 nm to about 10 nm.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the forming source/drain regions comprises depositing an epitaxial material in the enlarged recess.

6. A method for manufacturing a semiconductor device, comprising:

forming one or more fins extending in a first direction over a substrate,

wherein the one or more fins include at least one second region along the first direction and first regions on either side of each second region along the first direction;

forming a gate structure extending along a second direction overlying the second region of the fins, wherein the gate structure comprises:

a gate dielectric layer overlying the fin;

a gate electrode overlying the gate dielectric layer; and

a pair of insulating gate sidewalls formed on opposing lateral surfaces of the gate electrode extending along the second direction; and

removing a portion of the fins in the first regions to form recesses in the first regions;

forming uniformly doped regions in a surface of the recesses, wherein the uniformly doped regions are continuous regions that follow contours of the recesses;

removing the uniformly doped regions to form enlarged recesses; and

forming source/drain regions in the enlarged recesses,

wherein the source/drain regions extend under adjacent insulating gate sidewalls along the second direction.

7. The method for manufacturing a semiconductor device according to claim 6 , wherein the uniformly doped regions are formed by implanting a dopant into the surface of the recesses.

8. The method for manufacturing a semiconductor device according to claim 6 , wherein the uniformly doped regions are formed by conformal surface doping to form doped layers having substantially uniform thicknesses in the surface of the recesses.

9. The method for manufacturing a semiconductor device according to claim 8 , wherein the uniformly doped regions are formed by plasma doping.

10. The method for manufacturing a semiconductor device according to claim 8 , wherein the doped layers have a thickness of about 0.5 nm to about 10 nm.

11. The method for manufacturing a semiconductor device according to claim 6 , wherein a plurality of the second regions are formed on each fin, and the second regions and the first regions are alternatingly formed along the first direction.

12. The method for manufacturing a semiconductor device according to claim 11 , wherein a gate structure is formed over each second region.

13. The method for manufacturing a semiconductor device according to claim 6 , wherein the forming source/drain regions comprises depositing an epitaxial material in the enlarged recesses.

14. A method for manufacturing a semiconductor device, comprising:

forming an insulating layer over a plurality of spaced-apart gate structures overlying a fin, wherein the fin extends in a first direction,

and the gate structures extend in a second direction substantially perpendicular to the first direction;

etching a portion of the insulating layer between two adjacent gate structures to expose a first portion of the fin;

etching the first portion of the fin to form a recess in the fin;

conformally doping the surface of the recess to form a doped region;

selectively etching the doped region to remove the doped region, thereby forming an enlarged recess extending into a portion of the fin underlying the gate structures; and

forming a source/drain region in a surface of the enlarged recess where the doped region was removed.

15. The method for manufacturing a semiconductor device according to claim 14 , wherein the doped region has a substantially uniform thickness in the surface of the recess.

16. The method for manufacturing a semiconductor device according to claim 14 , wherein the doped region is formed by plasma doping.

17. The method for manufacturing a semiconductor device according to claim 14 , wherein the forming the source/drain region comprises depositing an epitaxial material in the enlarged recess.

18. The method for manufacturing a semiconductor device according to claim 14 , wherein the portion of the insulating layer is anisotropically etched.

19. The method for manufacturing a semiconductor device according to claim 14 , wherein the doped region is isotropically etched.