IP Library › Granted Patent US 10,062,761
Granted Patent B2
US 10,062,761 · App. 14/730,851 · Granted Aug 28, 2018

Method for manufacturing semiconductor device

Inventor: Atsushi Yoshimoto (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/4236H01L21/02233H01L21/26513H01L21/28035H01L21/768H01L29/0619H01L29/0696H01L29/407H01L29/66348H01L29/66734H01L29/7397H01L29/7813H01L21/02255H01L29/0692H01L29/42376
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Quick Facts
Patent No.
US 10,062,761
App. No.
14/730,851
Granted
Aug 28, 2018
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes steps of forming a trench in a surface of a semiconductor substrate of a first conductivity type in a depth direction; forming a conductive layer in the trench, with a first insulating film interposed therebetween; dividing the conductive layer into a gate electrode and an in-trench wiring layer which face each other in the trench and filling a gap between the gate electrode and the in-trench wiring layer with a second insulating film; introducing second-conductivity-type impurities into the entire surface of the semiconductor substrate to form a channel forming region of a second conductivity type; and selectively forming a main electrode region of the first conductivity type in a portion of the channel forming region which is provided along an opening portion of the trench so as to come into contact with the opening portion.

Claims (25)

1. A method for manufacturing a semiconductor device comprising:

forming a trench in a surface of a semiconductor substrate of a first conductivity type in a depth direction;

forming a conductive layer in the trench, with a first insulating film interposed therebetween, so as to be buried in the entire trench;

forming a third insulating film on the conductive layer;

forming an opening in the third insulating film;

etching the conductive layer, via the opening in the third insulating film, thereby dividing the conductive layer into a gate electrode and an in-trench wiring layer which face each other in the trench and filling a gap between the gate electrode and the in-trench wiring layer with a second insulating film, thereby covering at least a portion of the third insulating film that is not subsequently removed;

introducing second-conductivity-type impurities into the entire surface of the semiconductor substrate to form a channel forming region of a second conductivity type; and

selectively forming a main electrode region of the first conductivity type in a portion of the channel forming region which is provided along the trench so as to come into contact with the trench.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the channel forming region is formed before the conductive layer is divided.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein forming the channel forming region includes implanting second-conductivity-type impurity ions into the entire surface of the semiconductor substrate.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein forming the main electrode region includes selectively implanting first-conductivity-type impurity ions into the channel forming region.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the conductive layer is a polysilicon layer doped with impurities.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the first insulating film is formed by thermally oxidizing the semiconductor substrate, and the second insulating film is any one of an HTO film, an organic silicon compound film, a PSG film, and a BPSG film.

7. The method for manufacturing a semiconductor device according to claim 2 , wherein forming the channel forming region includes implanting second-conductivity-type impurity ions into the entire surface of the semiconductor substrate.

8. The method for manufacturing a semiconductor device according to claim 2 , wherein forming the main electrode region includes selectively implanting first-conductivity-type impurity ions into the channel forming region.

9. The method for manufacturing a semiconductor device according to claim 2 , wherein the conductive layer is a polysilicon layer doped with impurities.

10. The method for manufacturing a semiconductor device according to claim 2 , wherein the first insulating film is formed by thermally oxidizing the semiconductor substrate, and the second insulating film is any one of an HTO film, an organic silicon compound film, a PSG film, and a BPSG film.

11. The method for manufacturing a semiconductor device according to claim 1 , wherein the opening is formed in a portion of the third insulating film corresponding to a center of the trench.

12. The method for manufacturing a semiconductor device according to claim 2 , wherein the opening is formed in a portion of the third insulating film corresponding to a center of the trench.

13. The method for manufacturing a semiconductor device according to claim 1 , wherein when filling the gap between the gate electrode and the in-trench wiring layer with the second insulating film, the second insulating film is formed directly on the third insulating film.

14. The method for manufacturing a semiconductor device according to claim 1 , further comprising forming an electrode on the second insulating film.

15. The method for manufacturing a semiconductor device according to claim 1 , further comprising:

forming an opening portion in the second insulating film and the third insulating film; and

forming an electrode in the opening portion such that the electrode is formed directly on at least a sidewall of the second insulating film, a sidewall of the third insulating film, and the channel forming region.

16. The method for manufacturing a semiconductor device according to claim 1 , wherein when introducing the second-conductivity-type impurities into the entire surface of the semiconductor substrate to form the channel forming region of the second conductivity type, the second-conductivity-type impurities are introduced without using a mask.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2015
From: YOSHIMOTO, ATSUSHI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 035788/0540 →
Priority Claims (1)
JP 2013-114979 · May 31, 2013 · national
Continuity (2)
Continuation PCTJP2014002499 · May 12, 2014
Related Publication 20150270361A1 · Sep 24, 2015