Nonvolatile memory device including multiple planes
A nonvolatile memory device includes bit lines arranged in a first direction over a substrate; a memory cell array disposed between the substrate and the bit lines, and including a plurality of planes which are arranged in a second direction perpendicular to the first direction; page buffer circuits disposed between the substrate and the memory cell array; contact pads disposed between the substrate and the memory cell array, the contact pads being suitable for electrically coupling the bit lines and the page buffer circuits; and routing lines disposed at the same layer as the contact pads, and extending in the second direction, wherein the contact pads are disposed to overlap with at least two lines which are arranged in the second direction, and the routing lines are formed in a bent pattern to pass between the contact pads which are disposed to overlap with different lines.
1. A nonvolatile memory device comprising:
a plurality of bit lines arranged in a first direction over a substrate;
a memory cell array including a plurality of planes arranged in a second direction perpendicular to the first direction, the memory cell array disposed between the substrate and the bit lines in a third direction orthogonal to the first and second directions;
page buffer circuits disposed between the substrate and the memory cell array in the third direction;
contact pads disposed between the substrate and the memory cell array in the third direction, the contact pads being suitable for electrically coupling the bit lines and the page buffer circuits; and
routing lines disposed at the same layer as the contact pads, the routing lines extending in the second direction,
wherein the contact pads are disposed to overlap with at least two lines which are arranged in the second direction, and the routing lines are formed in a bent pattern to pass between the contact pads which are disposed to overlap with different lines.
2. The nonvolatile memory device according to claim 1 , wherein the contact pads correspond to the bit lines, respectively, and overlap with corresponding bit lines, respectively.
3. The nonvolatile memory device according to claim 1 , further comprising:
a peripheral circuit disposed between the substrate and the memory cell array, and arranged side by side with the page buffer circuits in the second direction; and
cache buffers disposed between the substrate and the memory cell array, arranged side by side with the page buffer circuits and the peripheral circuit in the second direction, and electrically coupled with the peripheral circuit through the routing lines.
4. The nonvolatile memory device according to claim 3 , wherein each of the cache buffers is disposed adjacent to the peripheral circuit in the second direction with at least one page buffer interposed therebetween.
5. The nonvolatile memory device according to claim 3 ,
wherein the page buffer circuits correspond to the planes, respectively,
wherein the cache buffers correspond to the planes, respectively, and
wherein each of the cache buffers is disposed adjacent to a page buffer circuit corresponding to the same plane with itself, in the second direction.
6. The nonvolatile memory device according to claim 5 , further comprising:
switch circuits corresponding to the planes, respectively, and electrically coupled to corresponding planes, respectively, through word line and select lines; and
row decoders corresponding to the planes, respectively, and electrically coupled to corresponding planes, respectively, through switch circuits corresponding to the same planes with themselves.
7. The nonvolatile memory device according to claim 6 ,
wherein each of the page buffer circuits comprises two sub-page buffer circuits which are physically separated from each other, and
wherein the sub-page buffer circuits included in each of the page buffer circuits are disposed adjacent to each other in the first direction with a switch circuit and a row decoder corresponding to the same plane with themselves, disposed therebetween.
8. The nonvolatile memory device according to claim 6 ,
wherein each of the cache buffers comprises two sub-cache buffers which are physically separated from each other, and
wherein the sub-cache buffers included in each of the cache buffers are disposed themselves each other in the first direction with a switch circuit and a row decoder corresponding to the same plane with themselves, disposed therebetween.
9. The nonvolatile memory device according to claim 3 , wherein the peripheral circuit comprises:
an input/output circuit suitable for transferring input data to the cache buffers or transferring output data from the cache buffers to an exterior;
a control logic suitable for generating cache input/output control signals; and
a column decoder suitable for generating a column decoding signal.
10. The nonvolatile memory device according to claim 9 , wherein the routing lines comprise:
data lines electrically coupled between the input/output circuit and the cache buffers, and suitable for transferring the input data and the output data;
cache input/output control signal lines electrically coupled between the control logic and the cache buffers, and suitable for transferring the cache input/output control signals to the cache buffers; and
column decoding signal lines electrically coupled between the column decoder and the cache buffers, and suitable for transferring the column decoding signal to the cache buffers.
11. A nonvolatile memory device comprising:
a plurality of bit lines arranged in a first direction over a substrate;
a memory cell array including a plurality of cell gate lines and a plurality of dielectric lines which are arranged in a second direction perpendicular to the first direction, the memory cell array disposed between the substrate and the bit lines in a third direction orthogonal to the first and second directions;
a page buffer circuit disposed between the substrate and the memory cell array in the third direction;
contact pads disposed between the page buffer circuit and the memory cell array in the third direction, and suitable for electrically coupling the page buffer circuit and the bit lines; and
routing lines disposed at the same layer as the contact pads, and extending in the second direction,
wherein the contact pads are disposed to overlap with at least two of the dielectric lines, and
wherein the routing lines are formed in a bent pattern to pass between the contact pads which overlap with different dielectric lines.
12. The nonvolatile memory device according to claim 11 ,
wherein each of the cell gate lines comprises cell gate conductive layers and first dielectric layers which are stacked alternately, and
wherein each of the dielectric lines comprises second dielectric layers and third dielectric layers which are stacked alternately.
13. The nonvolatile memory device according to claim 11 , further comprising:
contact plugs passing through the dielectric lines in a third direction that is orthogonal to the first direction and the second direction, and suitable for electrically coupling the contact pads and the bit lines.
14. The nonvolatile memory device according to claim 13 , further comprising:
a semiconductor layer disposed between the memory cell array and the contact pads; and
vertical channel layers passing through the cell gate lines in the third direction, and electrically coupled with the semiconductor layer.
15. The nonvolatile memory device according to claim 14 , wherein the semiconductor layer includes openings which overlap with the dielectric lines and through which the contact plugs pass.
16. A nonvolatile memory device comprising:
a plurality of bit lines arranged in a first direction over a substrate;
a memory cell array including a plurality of planes which are arranged in the first direction and a second direction perpendicular to the first direction, the memory cell array disposed between the substrate and the bit lines in a third direction orthogonal to the first and second directions;
page buffer circuits disposed between the substrate and the memory cell array in the third direction;
contact pads disposed between the page buffer circuits and the memory cell array in the third direction, and suitable for electrically coupling the bit lines and the page buffer circuits; and
routing lines disposed at the same layer as the contact pads, and extending in the second direction,
wherein the contact pads are disposed to overlap with at least two lines which are arranged in the second direction, and
wherein the routing lines are formed in a bent pattern to pass between the contact pads which are disposed to overlap with different lines.
17. The nonvolatile memory device according to claim 16 ,
wherein the page buffer circuits correspond to the planes, respectively, and
wherein each of the page buffer circuits is disposed below a corresponding plane.
18. The nonvolatile memory device according to claim 17 , further comprising:
a peripheral circuit disposed between the substrate and the memory cell array, and arranged side by side with the page buffer circuits in the second direction; and
cache buffers disposed between the substrate and the memory cell array, arranged side by side with the page buffer circuits and the peripheral circuit in the second direction, and electrically coupled with the peripheral circuit through the routing lines.
19. The nonvolatile memory device according to claim 18 ,
wherein the cache buffers correspond to the planes, respectively, and
wherein each of the cache buffers is disposed adjacent to a page buffer circuit corresponding to the same plane with itself, in the second direction.
20. The nonvolatile memory device according to claim 19 , further comprising:
switch circuits corresponding to the planes, respectively, and electrically coupled to corresponding planes, respectively, through select lines; and
row decoders corresponding to the planes, respectively, and electrically coupled to corresponding planes, respectively, through switch circuits corresponding to the same planes with themselves,
wherein each of the switch circuits is disposed adjacent to a page buffer circuit and a cache buffer corresponding to the same plane with itself, in the first direction, and
wherein each of the row decoders is disposed adjacent to a page buffer circuit and a cache buffer corresponding to the same plane with itself, in the first direction, with a switch circuit interposed therebetween.