Semiconductor device and method for fabricating the same
A semiconductor device includes a first fin-type pattern on a substrate, having a first sidewall and a second sidewall opposed to each other; a first trench formed in contact with the first sidewall; a second trench formed in contact with the second sidewall; a first field insulating layer partially filling the first trench; and a second field insulating layer partially filling the second trench and a second field insulating layer partially filling the second trench. The second field insulating layer includes a first region and a second region disposed in a sequential order starting from the second sidewall, an upper surface of the second region being higher than an upper surface of the first field insulating layer. The device further includes a gate electrode on the first fin-type pattern, the first field insulating layer and the second field insulating layer, the gate electrode intersecting the first fin-type pattern and overlapping the second region.
1. A semiconductor device, comprising:
a first fin-type pattern on a substrate, comprising a first sidewall and a second sidewall opposed to each other;
a first trench formed in contact with the first sidewall;
a second trench formed in contact with the second sidewall;
a first field-insulating layer partially filling the first trench;
a second field-insulating layer partially filling the second trench, and comprising a first region and a second region disposed in a sequential order starting from the second sidewall, an upper surface of the second region being higher than an upper surface of the first field-insulating layer; and
a gate electrode on the first fin-type pattern, the first field-insulating layer and the second field-insulating layer, the gate electrode intersecting the first fin-type pattern and overlapping the second region.
2. The semiconductor device of claim 1 , wherein a contact between the upper surface of the first region of the second field-insulating layer and the first fin-type pattern is lower than the upper surface of the second region of the second field-insulating layer.
3. The semiconductor device of claim 1 , wherein the second field-insulating layer further comprises a third region in contact with the second region, and
an upper surface of the third region is lower than the upper surface of the second region.
4. The semiconductor device of claim 1 , wherein a bottom surface of the first region is higher than a bottom surface of the second region.
5. The semiconductor device of claim 1 , wherein a width of the second region is greater than a width of the first region.
6. The semiconductor device of claim 1 , wherein the upper surface of the second region is higher than the upper surface of the first region.
7. The semiconductor device of claim 1 , wherein an uppermost portion of the upper surface of the second field-insulating layer is located at the second region.
8. The semiconductor device of claim 1 , further comprising a second fin-type pattern in contact with the second field-insulating layer, and in an opposite direction from the first fin-type pattern with reference to the second field-insulating layer.
9. The semiconductor device of claim 1 , wherein the upper surface of the first fin-type pattern is lower than an uppermost portion of the upper surface of the second field-insulating layer.
10. A semiconductor device, comprising:
a first and a second fin-type patterns spaced from each other;
a first trench between the first and the second fin-type patterns, spacing the first and the second fin-type patterns from each other;
a field-insulating layer formed within the first trench, in contact with sidewalls of the first and the second fin-type patterns, respectively; and
a gate electrode formed on the first fin-type pattern, the second fin-type pattern, and the insulating layer,
wherein the field-insulating layer comprises a first region and a second region, and
an upper surface of the first region is lower than an upper surface of the second region.
11. The semiconductor device of claim 10 , wherein the first region is disposed on both sides of the second region,
the first region is in contact with the first fin-type pattern and the second fin-type pattern, and
the second region is not in contact with the first and the second fin-type patterns.
12. The semiconductor device of claim 10 , wherein a thickness of the gate electrode overlapping the second region is less than a thickness of the gate electrode overlapping the first region.
13. The semiconductor device of claim 10 , wherein a contact between the upper surface of the field-insulating layer and the first fin-type pattern is higher than a portion of the upper surface of the first region.
14. The semiconductor device of claim 10 , further comprising a second trench formed in an opposite direction from the first trench with reference to the first fin-type pattern.
15. The semiconductor device of claim 10 , wherein a bottom surface of the first region is higher than a bottom surface of the second region.
16. A semiconductor device, comprising:
first, second and third fin-type patterns spaced from each other;
a first trench between the first and the second fin-type patterns, spacing the first and the second fin-type patterns from each other;
a second trench between the second and the third fin-type patterns, spacing the second and the third fin-type patterns from each other;
a first field-insulating layer partially filling the first trench;
a second field-insulating layer partially filling the second trench; and
a gate electrode formed on the first fin-type pattern, the second fin-type pattern, and the first and the second field-insulating layers,
wherein a first region of a lower surface of the gate electrode that overlaps the first field-insulating layer, is higher than a second region overlapping the second field-insulating layer.
17. The semiconductor device of claim 16 , wherein a width of the first trench is greater than a width of the second trench.
18. The semiconductor device of claim 16 , wherein a gap between the first and the second fin-type patterns is wider than a gap between the second and the third fin-type patterns.
19. The semiconductor device of claim 16 , wherein an uppermost portion of the lower surface of the gate electrode is located at the first region.
20. The semiconductor device of claim 16 , wherein the gate electrode is a single integrated structure.