Core frequency/count decision-based thermal mitigation optimization for a multi-core integrated circuit
Systems, methods, and computer programs are disclosed for providing optimal power/performance thermal mitigation in a portable computing device having a plurality of processing cores. An exemplary method comprises storing a power sweep table defining a power consumption value for each of a plurality of core frequency and core count combinations for an integrated circuit having a plurality of processing cores. A search table is generated by filtering the power sweep table based on one or more configuration parameters associated with the integrated circuit. A target power level is selected to sustain a thermal power envelope for the integrated circuit. The search table is traversed to find one of the plurality of core frequency and core count combinations having a corresponding power consumption value that matches the target power level.
1. A method for providing optimal power/performance thermal mitigation in a portable computing device having a plurality of processing cores, the method comprising:
storing a power sweep table defining a power consumption value for each of a plurality of core frequency and core count combinations for an integrated circuit having a plurality of processing cores;
generating a search table by filtering the power sweep table based on one or more configuration parameters associated with the integrated circuit;
defining a plurality of power scaling buckets, each power scaling bucket having a corresponding power level; and
for each power scaling bucket of the plurality of power scaling buckets, traversing the search table to find one of the plurality of core frequency and core count combinations having a corresponding power consumption value that matches the power level corresponding to the power scaling bucket, wherein traversing the search table comprises starting at a maximum core count and a maximum core frequency and searching decreasing core frequencies corresponding to the maximum core count, and if no matching power consumption value is found then decreasing the core count and searching decreasing core frequencies corresponding to the decreased core count.
2. The method of claim 1 , wherein the plurality of processing cores comprises a heterogeneous processor cluster architecture having at least a first processor with a first performance range and a second processor with a second performance range, the first performance range being less than the second performance range.
3. The method of claim 2 , wherein the heterogeneous processor cluster architecture comprises a unified power rail.
4. The method of claim 1 , wherein the one or more configuration parameters associated with the integrated circuit comprises one or more of a minimum performance floor, a number of cores, a chipset class type, a maximum power level, a number of available power levels, an offset between the available power levels, and one or more skin temperature specifications.
5. The method of claim 1 , wherein the power sweep table is generated in a pre-characterization process.
6. The method of claim 1 , wherein the plurality of power scaling buckets are dynamically calculated.
7. The method of claim 1 , wherein the portable computing device comprises one of a smart phone, a tablet computer, and a standalone virtual reality device.
8. A system for providing optimal power/performance thermal mitigation in a portable computing device having a plurality of processing cores, the system comprising:
means for storing a power sweep table defining a power consumption value for each of a plurality of core frequency and core count combinations for an integrated circuit having a plurality of processing cores;
means for generating a search table by filtering the power sweep table based on one or more configuration parameters associated with the integrated circuit;
means for defining a plurality of power scaling buckets, each power scaling bucket having a corresponding power level; and
means, for each power scaling bucket of the plurality of power scaling buckets, for traversing the search table to find one of the plurality of core frequency and core count combinations having a corresponding power consumption value that matches the power level corresponding to the power scaling bucket, wherein traversing the search table comprises starting at a maximum core count and a maximum core frequency and searching decreasing core frequencies corresponding to the maximum core count, and if no matching power consumption value is found then decreasing the core count and searching decreasing core frequencies corresponding to the decreased core count.
9. The system of claim 8 , wherein the plurality of processing cores comprises a heterogeneous processor cluster architecture having a unified power rail.
10. The system of claim 8 , wherein the one or more configuration parameters associated with the integrated circuit comprises one or more of a minimum performance floor, a number of cores, a chipset class type, a maximum power level, a number of available power levels, an offset between the available power levels, and one or more skin temperature specifications.
11. The system of claim 8 , wherein the means for defining a plurality of power scaling buckets comprises a means for dynamically calculating the plurality of power scaling buckets.
12. The system of claim 8 , wherein the portable computing device comprises one of a smart phone, a tablet computer, and a standalone virtual reality device.
13. A computer program embodied in a non-transitory computer-readable medium and executable by a processor for providing optimal power/performance thermal mitigation in a portable computing device having a plurality of processing cores, the computer program comprising logic configured to:
store a power sweep table defining a power consumption value for each of a plurality of core frequency and core count combinations for an integrated circuit having a plurality of processing cores;
generate a search table by filtering the power sweep table based on one or more configuration parameters associated with the integrated circuit;
define a plurality of power scaling buckets, each power scaling bucket having a corresponding power level; and
for each power scaling bucket of the plurality of power scaling buckets, traverse the search table to find one of the plurality of core frequency and core count combinations having a corresponding power consumption value that matches the power level corresponding to the power scaling bucket, wherein traversing the search table comprises starting at a maximum core count and a maximum core frequency and searching decreasing core frequencies corresponding to the maximum core count, and if no matching power consumption value is found then decreasing the core count and searching decreasing core frequencies corresponding to the decreased core count.
14. The computer program of claim 13 , wherein the plurality of processing cores comprises a heterogeneous processor cluster architecture having separate power rails.
15. The computer program of claim 13 , wherein the one or more configuration parameters associated with the integrated circuit comprises one or more of a minimum performance floor, a number of cores, a chipset class type, a maximum power level, a number of available power levels, an offset between the available power levels, and one or more skin temperature specifications.
16. The computer program of claim 13 , wherein the plurality of power scaling buckets are dynamically calculated.
17. The computer program of claim 13 , wherein the portable computing device comprises one of a smart phone, a tablet computer, and a standalone virtual reality device.
18. A system for providing optimal power/performance thermal mitigation in a portable computing device having a plurality of processing cores, the system comprising:
an integrated circuit comprising a plurality of processing cores:
a memory for storing a power sweep table defining a power consumption value for each of a plurality of core frequency and core count combinations for the integrated circuit; and
a core frequency/count thermal mitigation optimization module comprising logic configured to:
generate a search table by filtering the power sweep table based on one or more configuration parameters associated with the integrated circuit;
define a plurality of power scaling buckets, each power scaling bucket having a corresponding power level; and
traverse the search table to find one of the plurality of core frequency and core count combinations having a corresponding power consumption value that matches the power level corresponding to the power scaling bucket, wherein traversing the search table comprises starting at a maximum core count and a maximum core frequency and searching decreasing core frequencies corresponding to the maximum core count, and if no matching power consumption value is found then decreasing the core count and searching decreasing core frequencies corresponding to the decreased core count.
19. The system of claim 18 , wherein the plurality of processing cores comprises a heterogeneous processor cluster architecture having at least a first processor with a first performance range and a second processor with a second performance range, the first performance range being less than the second performance range.
20. The system of claim 19 , wherein the heterogeneous processor cluster architecture comprises a unified power rail.
21. The system of claim 18 , wherein the one or more configuration parameters associated with the integrated circuit are stored in a configuration file comprising one or more of a minimum performance floor, a number of cores, a chipset class type, a maximum power level, a number of available power levels, an offset between the available power levels, and one or more skin temperature specifications.
22. The system of claim 18 , wherein the portable computing device comprises one of a smart phone, a tablet computer, and a standalone virtual reality device.